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What is your most time-consuming task when testing an embedded system design?
Validating, troubleshooting serial or parallel communication buses
    10%
Validating memory system operation
    7%
Checking compliance with industry standards
    14%
Verifying system-level operation, interaction among components
    64%
Other
    5%
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    Partitioning an ASIC Design into Multiple FPGAs

    This article outlines the most common approaches and flows to consider before you embark on your next partitioning project. Ultimately, you can accelerate the verification phase by using an ASIC prototyping approach that allows you to build multi-FPGA based prototypes of ASIC designs in an intuitive fashion, with little or no modifications to the original design.


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    Single-key capacitive touch controllers target portables

    Atmel's new line of single-key touch controllers offers faster response time, low current consumption and low noise to enable next-generation designs.


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