No prudent chip company would admit as much to customers, but the unspoken truth in today's complex world of system-on-chip (SoC) design is that most ICs will neither be developed nor delivered on time.

In fact, 89 percent of IC development projects miss their deadlines, according to Ron Collett, president and CEO at Numetrics Management Systems.

Consulting firm Accenture reports a similar trend, citing a range of schedule delays from as little as 3 percent to as much as 30 percent in IC development. If the IC in question is a lead, first-generation product--that is, a new chip requiring a new design--it will typically register an additional 15 to 30 percent delay in the design schedule, compared with a less-complex second, third, fourth or fifth spin of an existing product, said Scott Grant, senior executive with Accenture's Semiconductor Business Practice.

No customer would knowingly tolerate such delays. Nor could a reputable chip manufacturer intentionally budget such chronic overruns, especially with the cost of IC development skyrocketing. Schedule slips in IC development often result in a semiconductor company's missing an entire product cycle, losing prized design wins and triggering dangerous financial reverses.

EE Times has learned that Numetrics today will unveil enterprise resource planning (ERP) software tools designed to calculate chip design complexity, quantify scheduled risk, and estimate schedules and staffing requirements. While conventional ERP tools from Oracle, SAP or Siebel are used in managing sales, manufacturing, and general and administrative functions in an enterprise, none have existed thus far for semiconductor R&D organizations.

Numetrics has signed a multimillion-dollar, multiyear corporatewide agreement with NXP Semiconductors for its ERP offering. Numetrics claims that "six of the top 10" chip companies are already using Numetrics tools.

How bad is it?
A survey conducted last year by Embedded Systems Design, a sister publication of EE Times, found that the average embedded (not IC) development project comes in 4.1 months late. Numetrics' data shows that schedule slips for IC development vary, but they average 44 percent.

The reasons managers and designers cite for such delays range from "the intellectual property [core] was late" and "EDA tools are inadequate" to "a key manager left the organization" and "specs have changed." Collett calls them "the usual suspects" of excuses.

But the crux of the issue is unpredictability.

"You can't predict how challenging new functional-unit blocks [in a chip] will be and how complex the integration will be," said Accenture's Grant. "In many of these first-generation products, we have no way, even with historical data, to gauge what the newness factor is."

Taming that unpredictability is where Numetrics hopes to cash in.

Instead of dealing with a variety of individual causes for delays, Numetrics' ERP software aims to look at the big picture. Collett developed the tool suite by leveraging the huge database the company has amassed since 2000 in the course of offering chip vendors services such as benchmarking IC development projects and measuring productivity against competitors.

Collett believes IC development can be modeled as "a stochastic process," if adequate statistical data is available.