Rick Merritt

12/10/2012 8:29 PM EST

IBM is prototyping server CPUs in a new 3-D ready, 22-nm process disclosed at IEDM as Intel shared details of its SoC work and talked privately about its costs and foundry business.
SAN FRANCISCO – Intel and IBM went head-to-head with their latest 22-nm technologies in back-to-back papers at the International Electron Devices Meeting (IEDM) here Monday (Dec. 10). Separately, a top Intel fab executive commented on increasing wafer costs and the company’s foundry business.

IBM said it is prototyping server processors in a new 3-D ready, 22-nm process technology it hopes will deliver 25 to 35 percent boosts over its 32-nm node. Intel retains an edge with several 22-nm chips already in volume production, and disclosure at IEDM of a variant of the process for SoCs for a wide range of applications.

The Intel paper showed support for “high drive current across the spectrum of leakage and a full suite of SoC tools,” Mark Bohr, head of Intel’s process technology development group, said in a brief interview. The process is geared for a much wider array of designs than that of IBM, he added.

Bohr said Intel’s 22-nm FinFET process is cost effective, contradicting report it is 30 to 40 percent more expensive than TSMC’s 28-nm planar process. The addition of FinFET adds only 3 percent to the cost of the process. Its use of 80-nm minimum feature sizes can be made with a single pass of 193-nm lithography tools, making it cost effective.

Projections from an IMEC keynote that 14-nm wafers will be 90 percent more expensive than 28-nm parts due to the lack of EUV lithography are inaccurate, Bohr asserted. The cost increase for 14-nm wafers at Intel “is nowhere near that,” he said.

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.

Separately, Bohr said Intel does have a growing foundry business that may include some higher volume applications than its current announced customers like FPGA startup Achronix. However, “we don’t intend to be in the general-purpose foundry business…[and] I don’t think the [foundry] volumes ever will be huge” for Intel, he said.
Intel’s 22-nm SoC process

Intel's paper laid out characteristics of Intel’s 22-nm process variation for SoCs (see chart below). It outperforms Intel’s 32-nm planar process by 20 to 65 percent and covers four orders of magnitude in leakage current, said co-author C.H. Jan.

The process provides 51 to 56 percent improvements in high voltage performance used for fast interfaces such Ethernet, HDMI and PCI Express. That’s more than twice the 20 percent boost typical in this area for a new Intel node, Jan said.

In addition, analog performance went up three-fold after declines in the past three nodes. Intel offers a small library of analog circuits tailored to the process including precision resistors, metal-in-metal capacitors and high Q inductors.

The process supports high and standard performance options as well as low and ultra low power ones. It also includes SRAM designs optimized for density, power and performance some of which now hit 2.6 GHz at 1V, up from 1.8 GHz at 32 nm.


Click on image to enlarge.
IBM ready for 3-D at 22 nm

Finally, Intel created two new transistor designs specifically for the 22-nm SoC variant. One is focused on low power and the other on high voltage for mixed-signal and analog circuits (see chart above).

For its part, IBM described its 22-nm process using partially depleted silicon-on-insulator. IBM “has prototyped a number of server processors” in the node that achieve latency below 1.5 ns and 750 MHz random clock cycles, said IBM researcher S. Narasimha.

Narasimha declined to give specifics of what IBM might achieve with the 22-nm node. However he did say the goal was to provide 25 to 35 percent boosts of the previous node which delivered server processors running up to 5.5 GHz and others with up to 80 Mbytes embedded DRAM.

IBM created an SRAM cell that measures 0.026 mm² using the process. It also power supplies at 1.2V across a 550 mm2 die area, he said.

The process provides up to 15 levels of metal. The lowest five levels use 80-nm features, similar to the Intel process, and the top two levels support through-silicon vias for 3-D stacks with memory chips.

IBM will deliver a separate paper Wednesday on its 3-D stacking work.


Click on image to enlarge.