Steve Teig is the President and CTO of Tabula and the inventor of Tabula's Spacetime 3-Dimensional Programmable Logic Architecture. Prior to co-founding Tabula, Steve was co-CTO of Cadence Design Systems. Steve joined Cadence through its acquisition of Simplex Solutions, where he was also CTO. At Simplex, Steve invented and led the technology development for the X Architecture, which radically improves chip design by pervasively incorporating diagonal wiring. Before joining Simplex, Steve co-founded two successful biotechnology companies: CombiChem, (later acquired by DuPont Pharmaceuticals), where he was CTO, and BioCAD, where he was CTO and, later, CEO. At CombiChem, Steve invented and led the development of the company's revolutionary Discovery Engine technology, with which CombiChem discovered pharmaceutical-lead compounds for 11 different therapeutic areas in only five years. At BioCAD, Steve led the design of Catalyst, which was the first widely used, pharmaceutical discovery software and is still a leading software package used worldwide.

In the 1980s, Steve spent several years in the EDA industry, where his work had a major impact still felt today. First, at Trilogy Systems in 1982, he invented compiled-code logic simulation and led the development of the first simulator based on that technology. Then, as CTO and co-founder of Tangent Systems in 1984 (which later became Cadence's very first acquisition), he invented the principal place-and-route algorithms for the Tancell and Tangate products. Tancell was the first commercial, timing-driven P&R system and the first to use analytical placement, among other distinctions. Tangate, which was the first commercial, sea-of-gates P&R system, became Cadence's Gate Ensemble and Cell-3 Ensemble products, which have cumulatively generated over $2 B in revenue. Steve received a BSEE and BSCS from Princeton University. He holds over 220 patents. In 2002, he broke Thomas Edison's record for the number of patents filed by an individual in a single year.

Today's System-on-Chip (SoC) devices involve multiple processors and multiple hardware accelerators in closely-coupled or networked topologies. In addition to tiered memory structures and multi-layer bus structures, these systems – which may be executing hundreds of millions to tens of billions of instructions per second – feature extremely complex software components, and this software content is currently increasing almost exponentially.

The "von Neumann architecture" for computers, which was popularized by the Hungarian American mathematician John von Neumann, has now dominated computing for more than 65 years. It is a masterpiece of simplicity: readily implemented in hardware, easily understood by software developers, and amenable to compilation from a wide variety of programming languages. Unfortunately, it achieves its simplicity from the fundamental, non-physical assumption that reading from a memory location takes negligible, constant time independent of the size of the memory.

Decades of innovation in computer architecture and compiler design for uniprocessors has masked some of the von Neumann computer's intrinsic latency. The power requirements for this disguise have become prohibitive, though, which has ended the long, exponential rise in uniprocessor clock frequency. Multi-core processors, the semiconductor industry's response, have the virtue that they can clearly be built, but no one knows how to program them! Further, they make the same negligible-latency assumptions as uniprocessors, but disguising that latency is now quadratically more difficult.

In his keynote presentation, Steve Teig will show that highly useful yet non-physical oversimplifications such as the von Neumann architecture have numerous historical precedents from which we can learn. These examples suggest that a more physically aware, non-von Neumann machine could offer significantly higher-performance and far more power-efficient computation. Steve will also present some thoughts on what such a machine might look like – hint: it is not an array of microprocessors! – and how one might program it. It is only by simultaneously approaching architecture, hardware, and software – seeing them as aspects of a cohesive whole as von Neumann did – that we can maximize our chances of going beyond von Neumann computing.

There is growing agreement on the value of using system-level descriptions of SoC designs. Today, such descriptions allow algorithm exploration, functional partitioning, and some rough estimates as to system, cost, size, power, and performance. However, only a few vendors support the ability for system-level descriptions to be synthesized into RTL, and these solutions often support only limited types of structures. Have we already seen the future of system-level design, or is there a real path to directly synthesizable system-level descriptions, reusable test benches, and accurate estimates of design characteristics from system-level code?

Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive

Panelists:

• Tom Feist, Sr. Director of Marketing, Xilinx, Inc.
• David C Black, ESL Practice Leader, XtremeEDA
• Harry Gries, ASIC and SoC Design Consultant
• George Harper, Vice President of Marketing, Bluespec, Inc.

In this 30-minute session, Max wants to hear about your biggest design successes. Have you battled through overwhelming odds to achieve success? Have you created an SoC so fast, or containing so many logic gates, or that does something so weird and wonderful that you're simply bursting to tell the world about it? In that case, this is the session for you.

Moderator: JClive (Max) Maxfield, Vice President, TechBites Interactive

Panelists:

Coming Soon!

Sponsored Chat: New Cost-saving Techniques for Resolving On-chip Memory Bandwidth and Efficiency Bottlenecks

Sonics will discuss innovative, cost-effective approaches for alleviating memory efficiency congestion in high-bandwidth applications (such as mobile video streaming in PMPs, Smart phones, HDTVs, Set-top-boxes, DVRs). Designers will learn how to significantly boost memory bandwidth utilization by up to 30% without additional memory costs, system degradation or system re-design.

Moderator: Alex Chao, Director, Corporate Application Engineering Sonics, Inc.

The choices for both sources and types of IP are extensive and can be quite confusing. There are numerous options for soft processor cores, IP blocks targeting signal processing, digital peripherals, communication functions, as well as hardware acceleration of algorithms. In this session, a diverse panel of industry experts will discuss the selection of products that can both simplify the implementation of these functions and significantly lower their system and energy costs.

Moderator: Dylan McGrath, Online Editor, EE Times

Panelists:

• Rick Tomihiro, Director of Marketing, Semiconductor IP, Xilinx
• Frank Ferro, Director, Product Marketing, Sonics, Inc.
• Brian Gardner, Marketing Group Director,Open Integration Platform, Cadence
• Kalar Rajendiran, Sr. Director of Marketing, eSilicon

The trends are real; there is more data than ever before and it needs to be processed as quickly as possible. System on a Chip designs are becoming more complex, integrate more diverse functionality, and must be delivered in record short time. For years FPGAs have been on the fringe of many SoC designs, used for prototyping and fixing problems to avoid re-spins. Those days are over; today's FPGAs match alternative technologies in nearly every conceivable benchmark; IO bandwidth, raw processing performance, logic capacity, power consumption, and set the bar when it comes to time-to-market and flexibility. And if you thought today's FPGAs are impressive wait until you see the future where programmable technology takes SoC design to a whole new level. This webinar will highlight FPGA technology available today from Xilinx; what FPGAs can do and why it's easier than ever to get started. The webinar also shows the future of programmable technology available from Xilinx and how it will change next generation SoC design in the not too distant future.

Presenter: Brent Przybus, Director of Platform Marketing, Xilinx

About the Presenter:

Brent Przybus is director of platform marketing with responsibility for the definition, development, and promotion of Xilinx's current and next generation platforms that align FPGA technology, design tools, IP, reference designs, and development and evaluation boards. Przybus joined Xilinx in 2001 and has over 15 years of marketing and engineering experience in the programmable logic industry. Prior to joining Xilinx, Przybus worked as an engineering manager in the advanced graphics and high-performance.

In this 30-minute session, Dylan wants to focus on design failures and the things that caused them. Were you involved with an SoC development project that crashed and burned? Did the design tools fail to live up to expectations? Did the silicon simply not function as planned? Or was the business model fundamentally flawed? If you have a tale of woe you'd care to share, then this is the session for you.

Moderator: Dylan McGrath, Online Editor, EE Times

Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks. There is a tremendous variety of software and hardware-assisted verification technologies available, but which will be the most effective for a particular project? What special verification tools and flows are available for ASIC and FPGA-based SoCs? Can point tools address any "EDA holes" in the large ASIC- and FPGA-based SoC design flows? Architecture-related verification, RTL debug, formal verification, and hardware-assisted verification technologies will all be considered in this session.

Moderator: Clive (Max) Maxfield, Vice President, TechBites Interactive

Panelists:

• JL Gray, Vice President, Verilab, Inc.
• Jack Donovan, Founder, SystematIC Design
• Brian Bailey, President, Brian Bailey Consulting
• Rajeev K. Ranjan, Chief Technology Officer, Jasper Design Automation