Why Johnny can't stand one-size-fits-all 3-D glasses Blog 12/29/2009 5 comments The CE industry always talks about offering "better experiences" via brighter, larger-screen flat-panel TVs or ever smaller mobile phones. If they really mean it, then, why are they forcing everyone to wear 3-D glasses which will be -- for most people -- an uncomfortable experience?
CES 2010: A wireless OK Corral Blog 12/17/2009 Post a comment Pre-CES is always a heady time in the wireless home video space, but never so much as this up-coming event, what with wireless LAN, 60 GHz, ultrawideband, standard and non-standard multimedia distribution schemes vying for attendees' attention--and dollars. So I sat down Asaf Avidan, VP of marketing for 'long-time' UWB chip provider, Wisair, to see where UWB stood--or if it even could find a toehold--in the fray.
Comment: FTC's compiler attack on Intel is thin Blog 12/17/2009 3 comments I am no lawyer, and indeed no processor designer or compiler author, but there is one aspect of the recently announced Federal Trade Commission suit that is being brought against chip giant Intel Corp. that, being embedded in processor engineering, is intriguing and appears weak.
Draft of FIPS 140-3 released Programmable Logic DesignLine Blog 12/16/2009 Post a comment NIST released for public comment the second draft of the proposed FIPS 140-3 government computer security standards, which contain requirements for resistance to power analysis attacks.
The life of a warhorse Industrial Control DesignLine Blog 12/15/2009 2 comments There used to be a time some 35 years ago when a company called Zilog was respected for being the cool kid on the block. What hath 35 years wrought?
Lowering test costs in the nanometer era Blog 12/15/2009 Post a comment In this week's Guest Blog, Sanjiv Taneja, Vice President, Encounter Test, Cadence Design Systems, Inc., highlights the need to focus on Design for test (DFT) with a more holistic view of the economics of test.
IEDM: Organic growth for industrial use Industrial Control DesignLine Blog 12/9/2009 Post a comment At the International Electronics Devices Meeting, Holst Centre, imec and TNO presented a paper on what they claim to be the world-first organic transponder circuit with a bit rate of 50kbits/s. This bit rate approaches the requirements for the Electronic Product Coding (EPC) standards.
Panelists question fabless model viability Blog 12/4/2009 Post a comment Is fabless still fabulous? In a panel session at the IP-ESC 2009 Conference this week in Grenoble, France, panelists discussed the evolution of semiconductor business models and confronted views on whether the fabless model is dead or alive and kicking.
The SoC in 2020: Advances to redefine how we live Signal Processing DesignLine Blog 12/3/2009 Post a comment In this fourth installment of TI's 2020 Vision series, Senior Fellow Bill Witowsky (retired) explains why the inherent functionality of future high-performance SoCs will be defined by software in order to facilitate the repurposing required to offset their development costs.
Sensing the future Industrial Control DesignLine Blog 12/1/2009 Post a comment In the near future, experts predict silicon sensors will be everywhere, not only within electronic products and gadgets, but even inside the human body.
Blog Make a Frequency Plan Tom Burke 17 comments When designing a printed circuit board, you should develop a frequency plan, something that can be easily overlooked. A frequency plan should be one of your first steps ...