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Power DesignLine Blog
Content posted in March 2009
Ever hear of CQC?
Power DesignLine Blog  
3/30/2009   Post a comment
Bernard Murphy, Chief Technology Officer of Atrenta Inc., wants to make chip designers aware of continuous quality control.
How's your job?
Power DesignLine Blog  
3/25/2009   Post a comment
TechInsights, the company behind the Embedded Systems Conference and the publisher of EE Times, recently conducted a poll among people who will be attending the upcoming Embedded Systems Conference in San Jose which begins on March 30th.
Semiconductors build 'smart ' power
Power DesignLine Blog  
3/18/2009   Post a comment
There's a wealth of innovation that can be applied to power management as the job moves toward building out "smart grids".
Video: Digital power controller reference design
Power DesignLine Blog  
3/11/2009   1 comment
Analog Devices designed the board both because a PFC stage in an AC/DC supply outputs a DC voltage around 380VDC, and as a design that might fit in a high-voltage DC distribution architecture.
Video: Freescale demonstrates DC/DC harvester
Power DesignLine Blog  
3/4/2009   Post a comment
With a battery being charged at the output, the Freescale DC/DC converter outputs 3.8V, and delivers 63 mA to the load.


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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