Structured ASICs are cool! Programmable Logic DesignLine Blog 10/17/2005 Post a comment In addition to CPLDs, FPGAs, FPAAs, FPNAs, and programmable processors, Programmable Logic Designline is also going to cover Structured ASICs.
Microchip’s DSP PICs: Whatever next? Programmable Logic DesignLine Blog 10/14/2005 Post a comment You can only imagine my surprise to hear that those clever little rapscallions at Microchip are now selling 16-bit PIC microcontrollers with DSP-centric functionality!
Who is that masked man? Programmable Logic DesignLine Blog 10/12/2005 Post a comment I’m currently bouncing off the walls with excitement, because this is my first day to officially take the reins as the editor of this mega-cool site.
Xilinx FPGA-powered Ghostrider competes in DARPA Programmable Logic DesignLine Blog 10/7/2005 Post a comment I love zoomy applications--and this one is literally one of the zoomiest I've seen. Xilinx Spartan-3 and Virtex-II Pro FPGAs are at the heart of an autonomous vehicle's vision algorithm, allowing the vehicle to 'see' its surroundings, even in adverse conditions.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments