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Programmable Logic DesignLine Blog
Content posted in October 2005
The great day draws nigh...
Programmable Logic DesignLine Blog  
10/31/2005   Post a comment
Only three days to go to the first in a series of six FPGA seminars hosted by the IEEE in Boston.
Are they playing our tune?
Programmable Logic DesignLine Blog  
10/27/2005   Post a comment
Cool website locates the number one song playing on the day you were born.
Cool tool aids paralyzed engineers
Programmable Logic DesignLine Blog  
10/26/2005   Post a comment
An incredible piece of FREE software called Dasher helps people communicate and remain productive.
Cool "stuff" from Actel, Altera, and Xilinx
Programmable Logic DesignLine Blog  
10/24/2005   Post a comment
In the schematics for an old computer I found a "Banana Register" (because the data came in bunches)...
ChipX save us from being frozen in silicon!
Programmable Logic DesignLine Blog  
10/20/2005   Post a comment
One of the big problems with creating a standard cell ASIC is that your algorithms are largely "frozen in silicon."
If I had a coconut for every ...
Programmable Logic DesignLine Blog  
10/18/2005   Post a comment
The IEEE in Boston are hosting a series of six FPGA Seminars starting on Thursday 3rd November, 2005.
Structured ASICs are cool!
Programmable Logic DesignLine Blog  
10/17/2005   Post a comment
In addition to CPLDs, FPGAs, FPAAs, FPNAs, and programmable processors, Programmable Logic Designline is also going to cover Structured ASICs.
Microchip’s DSP PICs: Whatever next?
Programmable Logic DesignLine Blog  
10/14/2005   Post a comment
You can only imagine my surprise to hear that those clever little rapscallions at Microchip are now selling 16-bit PIC microcontrollers with DSP-centric functionality!
PicoChip's field-programmable node arrays (FPNAs)
Programmable Logic DesignLine Blog  
10/13/2005   Post a comment
I've been watching picoChip with interest since those days when they were running silent and deep in "secret squirrel" mode...
Who is that masked man?
Programmable Logic DesignLine Blog  
10/12/2005   Post a comment
I’m currently bouncing off the walls with excitement, because this is my first day to officially take the reins as the editor of this mega-cool site.
Xilinx FPGA-powered Ghostrider competes in DARPA
Programmable Logic DesignLine Blog  
10/7/2005   Post a comment
I love zoomy applications--and this one is literally one of the zoomiest I've seen. Xilinx Spartan-3 and Virtex-II Pro FPGAs are at the heart of an autonomous vehicle's vision algorithm, allowing the vehicle to 'see' its surroundings, even in adverse conditions.


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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