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Programmable Logic DesignLine Blog
Content posted in December 2012
Happy, inspiring video – "Bring Me Sunshine"
Programmable Logic DesignLine Blog  
12/20/2012   4 comments
Someone just sent out a link to a really good video that made me feel really happy (I'm still smiling as I pen these words)
System Hyper Pipelining = 16 MCU cores on a Spartan-6 LX9 FPGA
Programmable Logic DesignLine Blog  
12/20/2012   11 comments
My friend Tobias has been working on a rather cool technology called System Hyper Pipelining in which he uses registers to multiply the functionality of IP cores.
Altium introduces “Ideas”
Programmable Logic DesignLine Blog  
12/20/2012   1 comment
I just received news of a rather interesting offering from those clever guys and gals at Altium…
Energy harvesting + sensor network nodes = autonomous sensor network nodes
Programmable Logic DesignLine Blog  
12/20/2012   2 comments
My friend Luiz would like to share his paper that introduces the non-specialized reader to two combined technologies: energy harvesting and sensor network nodes.
TI and University of Florida student collaborate on FRAM research
Programmable Logic DesignLine Blog  
12/19/2012   1 comment
I just heard about a rather interesting university research story that improved upon the FRAM technology used in TI’s MSP430 Wolverine platform.
Union Jack vs. Union Flag
Programmable Logic DesignLine Blog  
12/7/2012   12 comments
I'm always interested in discovering something new, and I am now embroiled in a delightful morass of "stuff."
Don’t talk to me about Windows 8!
Programmable Logic DesignLine Blog  
12/5/2012   70 comments
Arrgggh! My wife just bought a new PC loaded with the Windows 8 operating system. I tried to wrap my brain around it and now my head hurts!
Cypress to host virtual worldwide embedded design conference
Programmable Logic DesignLine Blog  
12/3/2012   Post a comment
The PSoC virtual event on December 12 and 13 will offer 24 hours of programming on new design techniques, hot applications, and expert design panels.
"Best of 2012" Aldec Webinars Available Online
Programmable Logic DesignLine Blog  
12/3/2012   Post a comment
I must admit that some of these titles look rather interesting…


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9/25/2016
4:48:30 PM
michigan0 Sang Kim First, 28nm bulk is in volume manufacturing for several years by the major semiconductor companies but not 28nm FDSOI today yet. Why not? Simply because unlike 28nm bulk the LDD(Lightly Doped Drain) to minimize hot carrier generation can't be implemented in 28nm FDSOI. Furthermore, hot carrier reliability becomes worse with scaling, That is the major reason why 28nm FDSOI is not manufacturable today and will not be. Second, how can you suppress the leakage currents from such ultra short 7nm due to the short channel effects? How thin SOI thickness is required to prevent punch-through of un-dopped 7nm FDSOI? Possibly less than 4nm. Depositing such an ultra thin film less then 4nm filum uniformly and reliably over 12" wafers at the manufacturing line is extremely difficult or not even manufacturable. If not manufacturable, the 7nm FDSOI debate is over!Third, what happens when hot carriers are generated near the drain at normal operation of 7nm FDSOI? Electrons go to the positively biased drain with no harm but where the holes to go? The holes can't go to the substrate because of the thin BOX layer. Some holes may become trapped at the BOX layer causing Vt shift. However, the vast majority of holes drift through the the un-dopped SOI channel toward the N+Source,...
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