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Programmable Logic DesignLine Blog
Content posted in February 2012
The best FPGA papers of all time!
Programmable Logic DesignLine Blog  
2/22/2012   5 comments
The ACM/SIGDA Technical Committee has released a list of the best papers of the FPGA Symposium
How It Was: Fiddling and twiddling with the TV controls
Programmable Logic DesignLine Blog  
2/2/2012   21 comments
In the not-so-distant past you had to constantly fiddle and twiddle with your television's controls to keep a reasonable picture on the screen...
The Winter 2012 issue of Xcell Journal magazine is available now
Programmable Logic DesignLine Blog  
2/2/2012   Post a comment
The folks from Xilinx have just announced the immediate availability of the Winter 2012 edition of their quarterly Xcell Journal magazine


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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