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Content posted in May 2009
Shameless plug
Programmable Logic DesignLine Blog  
5/27/2009   Post a comment
This is just a note to encourage anyone who hasn't checked out Max Maxfield's Fundamentals of Mixed-Signal FPGAs course to do so without delay.
The design debate: Art versus science
Programmable Logic DesignLine Blog  
5/20/2009   4 comments
Ask a chip designer if the work he or she does is an art or a science and you will more than likely hear the former. But Naveed Sherwani, the outspoken president and CEO of fabless ASIC vendor Open-Silicon, takes issue with that.
What does software firm want with MathStar?
Programmable Logic DesignLine Blog  
5/13/2009   Post a comment
Why is PureChoice Inc., a vendor of building-performance reporting software, trying to buy MathStar for around $9.5 million? And why hasn't the defunct programmable logic vendor's board responded?
Patent strike?
Programmable Logic DesignLine Blog  
5/6/2009   Post a comment
In case you've missed it, there has been a fascinating exchange about the broken U.S. patent system taking place on the pages of EE Times over the past couple weeks.


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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