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Programmable Logic DesignLine Blog
Content posted in July 2009
ESL/HLS buzz at DAC
Programmable Logic DesignLine Blog  
7/30/2009   1 comment
The buzz over electronic-system level design and high-level synthesis seems to have reached a new level at this year's Design Automation Conference.
FPGA nuggets from 2009 Embedded Market Study
Programmable Logic DesignLine Blog  
7/23/2009   1 comment
There was some interesting data about FPGA to emerge from Embedded Systems Design magazine's 2009 Embedded Market Study, presented a couple of months back on TechOnline.
CSwitch shutdown confirmed
Programmable Logic DesignLine Blog  
7/3/2009   Post a comment
CSwitch President and CEO Doug Laird confirmed that the company halted operations in the last few weeks in an effort to conserve cash as it entered negotiations with potential buyers.
Video: Inside CSwitch headquarters
Programmable Logic DesignLine Blog  
7/2/2009   1 comment
Tired of being stonewalled by CSwitch executives, Mark LaPedus and I stopped by CSwitch's headquarters Wednesday on a quest for answers. Unfortunately, we didn't get many.
Is CSwitch dead?
Programmable Logic DesignLine Blog  
7/1/2009   Post a comment
FPGA startup CSwitch appears to have closed its doors, according to several industry sources.


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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