Optimal team sizes for chip projects Blog 2/28/2011 Post a comment Chip design projects demand a threshold number of engineers to meet schedule targets, yet, there's a point at which adding resources yields little, if any, additional development throughput.
Report from EDSFair 2011 Blog 2/25/2011 Post a comment At this year's ESDFair, EVE SA (Palaiseau, France) conducted a survey to determine chip design and verification trends in Japan. Check out what attendees told EVE's booth staff!
The end of American motors Blog 2/24/2011 28 comments The last domestic motor manufacturer is now in foreign hands. On top of it, imported motors are not meeting energy-efficiency requirements here in the land where such design considerations first emerged. Just what’s going on?
Let go of my Legos Blog 2/18/2011 12 comments Bill Neifert, Carbon's CTO, compares the design of today's SoCs with Lego bricks and outlines the analogies between the two seemingly disparate markets, from product strategy and development, product packaging and marketing to business models.
Seven can't miss highlights at ISSCC Blog 2/16/2011 12 comments Don Scansen has gone over the International Solid-State Circuits Conference advanced program with a fine-tooth comb to uncover seven gems that all attendees should have on their list.
The white screen of death... Blog 2/16/2011 27 comments I am not a happy person at the moment. The radiance of my smile is no longer lighting the world around me because earlier today, with no warning whatsoever, my computer gave up the ghost...
I want my own Jet Pack!!! Blog 2/12/2011 9 comments I know that the use of three exclamation marks (as in the title to this blog) is the sign of a deranged mind ... but I don’t care ... I want my own personal Jet Pack!!!
Standard design constraints: The next productivity boost for custom design Blog 2/11/2011 6 comments Manual design methodologies are no longer sufficient for custom designs as they begin to target 45nm-and-below process methodologies. Mark Waller, VP Engineering at Pulsic, Ltd., urges the custom-design community to work together and deliver a design constraints standard that will enable all custom design teams to maximize productivity gains.
Learn to optimize opamps Blog 2/10/2011 Post a comment OnFebruary 9th at noon eastern time Analog Devices will be running a 60minute webcast that explains the different types of operational amplifiers, their basic function and describe how engineers can select the right op amp for their circuit design.
What a relief Blog 2/10/2011 6 comments When you gotta go, you gotta go, but there are ways to modify one's behavior
Teaching an old dog (me) new tricks Blog 2/10/2011 24 comments Have you seen those things called ‘The Great Courses’? These are college-level courses that are available on DVD for you to study from the comfort of your sofa. I just ordered three...
So, what would you do? Blog 2/8/2011 1 comment Speaking of human mirrors, did you see…? And what about...? And you must have seen…! So what do you think you would do if you were ever faced with a situation like...?
The future is High-Level Synthesis Blog 2/4/2011 13 comments The future is high-level synthesis (HLS). According to Sean Dart, president and CEO, Forte Design Systems Inc., HLS will replace the register transfer level (RTL) as the predominant front-end design methodology and will be used to do everything logic synthesis can do today.
Amazingly cool trick with Windows 7 Blog 2/3/2011 55 comments Someone just showed me an amazingly cool trick with Windows 7 that’s going to save me a whole bunch of time (and frustration) in the days, weeks, months, and years to come...
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments