Spoof: Top 10 fears of today’s engineers Blog 7/29/2010 1 comment It’s that time of the year again when engineers air their most secret fears in the darkest corners of the forest. This time, though, a journalist was lurking in the woods and heard the secret whispers of some engineers, including an unidentified freshly minted engineer and a mid-career engineer at an unknown company.
The ripple effect Blog 7/29/2010 8 comments Part of the reason so many semiconductor projects miss schedule is that staffing levels are not aligned with the level of complexity that the design team needs to undertake. This is solvable problem.
Musings about Tabula and other FPGA startups Blog 7/28/2010 6 comments It has been a bad few weeks for FPGA startups. Tier Logic and Abound Logic (M2000) closed the doors, both apparently unable to get funding to continue. After some prodding from several high tech journalists, some bloggers, and a slew of calls from investor/wall street types, I started looking into the Tabula FPGA technology.
Protect your goal with post-silicon formal verification Blog 7/20/2010 5 comments SoC designers are learning the benefits of applying high-capacity formal verification techniques at every stage of the design. Our formal tools are powerful and versatile enough for a wide variety of tasks such as architectural exploration and RTL verification, all the way through post-silicon debug.
Emerging trends in embedded systems and applications Blog 7/18/2010 4 comments The embedded systems industry was born with the invention of microcontrollers and since then it has evolved into various forms, from primarily being designed for machine control applications to various other new verticals with the convergence of communications.
It’s Applegate, not 'antennagate' Blog 7/17/2010 10 comments The iPhone 4 antenna controversy was a minor problem but it highlights the need for Apple Inc. to develop a better system of managing issues related to the company’s public image than it has so far demonstrated.
Hubris, lessons from an Apple antenna debacle Blog 7/16/2010 17 comments Apple Inc. is paying a hefty price in lost market value and erosion of its image for not listening to its own engineer and others from a service provider who warned the design of the iPhone 4 could hurt signal reception.
Dispelling the myths of High-Level Synthesis Blog 7/15/2010 5 comments High-level synthesis (HLS) has been a hot topic for about the last 10 years, characterized as Electronic System Level (ESL) synthesis, algorithmic synthesis, and behavioral synthesis, and C synthesis by some. I just call it “simply, a better way to design hardware.”
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments