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Content tagged with Industrial Control Designline posted in December 1998
High Bandwidth Systems for High Performance DSP Applications
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12/17/1998   Post a comment
What do you do when your future applications are more complex, and involve handling lots of data in real time while managing computationally demanding processes. More processors, faster processors, more memory, and of course, a faster system bus. Or multiple buses handling multiple tasks. This article by Mercury Computer Systems' Gerard Vichniac talks about the RACE architecture and how it is likely to evolve in the marketplace over the next year or two.
Interview: Core pioneer head looks ahead
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12/14/1998   Post a comment
While the mainstream semiconductor industry is enduring hard times, ARM Holdings plc (Cambridge, England) and a pioneer of intellectual-property core licensing through its series of ARM 32-bit microprocessors, has had a barnstorming year.
Qualis debuts Web-based design reuse guide
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12/14/1998   Post a comment
A new resource for system-on-chip design debuts this week, as consulting firm Qualis Design Corp. announces a user-configurable, Web-based Reuse Methodology Field Guide. The document represents a novel approach to Internet-based publishing.
Sharp taps Cadence for processor core
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12/11/1998   Post a comment
Cadence Design Systems Inc. will redesign Sharp Corp.'s Data Driven Media Processor (DDMP) into a reusable core compliant with the Virtual Socket Interface Alliance standard as part of a long-term agreement between the two companies announced last week. The project is due to be completed next October, though the two companies will release tentative results in June.
Philips rolls out design reuse strategy
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12/9/1998   Post a comment
Philips Semiconductors is rolling out a corporate-wide "platform strategy"that seeks to deploy a common design methodology and common process technologies among all groups within the company. The strategy is a linchpin of Philips' effort to build a successful business model for reusable hardware and software.
Web-based metric evaluates IP cores
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12/8/1998   Post a comment
Synopsys Inc. has released its Web-based IP Catalyst Measure of Reuse Excellence (More) rating system, which looks to give customers a metric for evaluating the quality of cores.
Group confronts commingling of configurable cores
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12/4/1998   Post a comment
A new group is quietly forming to address what members believe is overlooked work: the software development required to create a common platform for the delivery of configurable cores from multiple vendors. Executives from ten companies will try to hammer out a plan when they convene at the DesignCon conference here in February.
Feature: Design reuse rules at TI's ASIC operation
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12/3/1998   Post a comment
DSPs may be king at Texas Instruments Inc., but they share the crown with the company's ASIC division, where design-for-reuse has been the ruling principle for several years.
Feature: Japan struggles with design reuse in SOC era
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12/3/1998   Post a comment
At a time of economic uncertainty and slumping demand for commodity semiconductors, Japan's electronics giants have turned to the system-on-chip (SOC) model as their saving grace. And they've put reusable intellectual property (IP)-developed in-house or acquired-at the top of their agendas to tackle ever-increasing design complexity for deep-submicron devices.
Analysis: Japan steel giants steer new semi course
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12/2/1998   Post a comment
In the early 1990s Japan's mammoth steel companies looked to semiconductors as a broad avenue for diversification. But the companies never achieved the revenue levels of the semiconductor giants, and the recent memory price plunge has battered many chip divisions. The steel majors now are exploring various strategies to reconstruct their semiconductor businesses. But whatever path they choose, they are not likely to find it easy going, analysts warned.
Feature: Europe builds core libraries for 'new' designers
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12/1/1998   Post a comment
Today's chip-design groups are becoming the intellectual-property (IP) core library builders of tomorrow. At least, that's the way it seems, with the design community splitting between core developers and a new class of engineer who brings those cores together quickly to create yet more complex ICs.
Feature: Design reuse is a matter of methods and tools
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12/1/1998   Post a comment
With the current emphasis on system-on-chip design, almost every new EDA tool seems to carry a "made-for-intellectual property" label. But users are finding that what's really important is not the tools themselves, but the methodology they permit.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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