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Content tagged with Industrial Control Designline posted in June 1999
Avant! alters IP plans; Cypress buys Arcus
News & Analysis  
6/30/1999   Post a comment
Fearing competition with its customers in the silicon intellectual property (IP) arena, Avant! Corp. has tabled its Galax! subsidiary and is preparing to roll out a new IP partnership program with its customers, EE Times has learned. As part of that change, Avant! has decided that it will not complete its planned purchase of Arcus Technology Ltd., an IP provider based in Bangalore, India.
Japan consortium looks to build IP distribution network
News & Analysis  
6/30/1999   Post a comment
Attempting to address a missing link in the burgeoning intellectual property (IP) trade, four Japan-based semiconductor and consumer electronics companies and the Japanese subsidiary of one U.S.-based EDA vendor have agreed to develop an electronic distribution and exchange network for IP cores.
'Jazz' plays for media stream audience
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6/29/1999   Post a comment
The Jazz architecture was designed with several goals in mind. Our target market-applications rich in data and computation such as video, audio and image processing-required an architecture with a high capacity for data throughput and a high performance rating.
Mentor gives automation boost to system-on-chip design
News & Analysis  
6/22/1999   Post a comment
Claiming a major step forward for design reuse, Mentor Graphics Corp. rolled out its QuickUse Development System at the Design Automation Conference (DAC) on Tuesday (June 22). By providing an infrastructure that automates many aspects of intellectual-property (IP) selection, integration, verification and implementation, QuickUse is claimed to have reduced design times at Toshiba Corp., its first customer, from months to days.
ARC teams processor with Mosaid DRAM
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6/22/1999   Post a comment
Mosaid Technologies Inc. (Ottawa, Canada), a design house, is teaming up with ARC Cores Ltd. (London) to promote system-on-a-chip (SoC) design based around ARC's 32-bit configurable processor.
Early users of IP cores could gain an edge from design reuse
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6/22/1999   Post a comment
Most systems companies are not benefiting from design reuse, and early attempts to adopt the approach are "mostly bad experiences," according to Dataquest Inc. As a result, ASIC vendors and independent design houses — currently the most likely reusers of intellectual property (IP) cores and the widest licensors of IP cores — stand to get the most benefit from design reuse, Dataquest said. As such, these companies could build up a design productivity advantage over systems companies o
Synopsys, Mentor release second edition of RMM
News & Analysis  
6/21/1999   Post a comment
Mentor Graphics Corp. and Synopsys Inc. released a second edition of the Reuse Methodology Manual (RMM), the seminal the reference book on design reuse, at this year's Design Automation Conference.
Cadence publishes guide to design reuse
News & Analysis  
6/21/1999   Post a comment
Following the lead set by Mentor Graphics Corp. and Synopsys Inc. with their Reuse Methodology Manual (RMM), Cadence Design Systems Inc. has announced the publication of a how-to book for design reuse. Titled "Surviving the SoC Revolution: a Guide to Platform-Based Design," the book is being previewed at this week's Design Automation Conference.
Helping LCD modules run from 3 V
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6/8/1999   Post a comment
Right tool mix shaves product cycle
News & Analysis  
6/8/1999   Post a comment
Portable wireless product makers are asked to design and build 30 to 50 new products per year-"products" being anything from simple software changes to major new device platforms. And they have to service various combinations of all of the different air-interface requirements in the world, from GSM and AMPS to CDMA and TDMA-with 3G and W-CDMA coming up quickly.
Circuit optimizer aims at efficiency
News & Analysis  
6/8/1999   Post a comment
Even with the help of highly specialized tools that cover all of the facets of a design flow, the critical act of designing at the transistor level is still performed with a rough balance of designer experience-which has no substitute-trial and error, and analog simulators. Analog simulators are as good as the information provided to them, so the heuristic methodology used in the design process can be identified as the root of much of the time and frustration experienced in a design cycle.
Synthesis proves to be Holy Grail for analog EDA
News & Analysis  
6/8/1999   Post a comment
Analog synthesis-the ability to construct efficient analog circuits from top-level descriptions-has become the holy grail of analog tool development. But the researchers pushing the envelope in synthesis are not to be found in whizzy corporate labs. They are largely university people, toiling away on shoestring budgets and stubborn determination.


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