Securing WLAN Links: Part 3 News & Analysis 7/30/2002 Post a comment There's no escaping that WEP is a problem for WLAN designers. In the final part of this series, we'll layout some technology solutions that can help designers enhance security in WLAN systems.
Scaling Optical Modules to 40-Gb Speeds News & Analysis 7/29/2002 Post a comment The call for 4X or 10X speed increases in datacom designs forces optical module manufacturers to evaluate new process technologies, better manage signal integrity, and account for imperfect performance in the existing fiber plant.
Relaxed rules proposed for early 65-nm processes News & Analysis 7/25/2002 Post a comment Chip designers planning to scale their system-on-chip designs to the 65-nanometer process technology node by the middle of the decade were given fair warning at Semicon West this past week: Steering past delays in lithography, interconnects and other elements crucial to extending Moore's Law will require some tricky navigation.
Rendering hair and fur needs computer graphics muscle News & Analysis 7/24/2002 Post a comment Before they became a checklist item for SoC designs, RAMDACs would convert digital RGB values to a value that lit a CRT phosphor dot - and the rendering engine came up with each RGB value was equivalent to a time-share on a Cray supercomputer. The times have changed, says this computer graphics authority, all the work is done by a single chip - cheap enough to power a kid's gaming machine. Here's how it works. . . using hair and fur as an example.
The Complexities of Designing Compilers for Protocol Stacks News & Analysis 7/24/2002 Post a comment Communication protocols, used to differentiate and to introduce new features into end products, require several attributes, including reusability, portability, and reliability. Novilit's Vladimir Novikov discusses the complex job of designing compilers for communication-protocol stacks.
Securing WLAN Links: Part 2 News & Analysis 7/23/2002 Post a comment The 802.11 specification has some clear authentication discrepancies that create security headaches for WLAN design engineers. In Part 2 of this series, we'll examine the 802.11 authentication mechanisms and the security problems they provide.
Real data cuts timing mumbo-jumbo for cascaded PLL designs News & Analysis 7/10/2002 Post a comment PLLs provide the designer with the luxury of re-timing late or early clocks, eliminating the propagation delays that occur when clocks are transported over long distances. But typically there is noise and degradation - jitter - with each PLL in the chain, says this Cypress clocking expert. Here is an excellent example of timing budget measurements that can reduce the impact of noise in your system.
VSIA guidelines assist SoC Signal Integrity News & Analysis 7/9/2002 Post a comment Authors and integrators of intellectual property (IP) are trying to tape out chips without real verification of chip-level signal integrity matters. EDA solutions are complex and inadequate, with capacity-limited extraction tools that run out of steam well before system-on-chip (SoC) design sizes are met.
Satisfying cell phone-PDA combo devices' need for multiple voltages News & Analysis 7/8/2002 Post a comment EE Times did not have room to print all the material we collected for its July 8th power management section - a contributed article package devoted to the engineering issues associated with extending battery life in merged cell phones and PDAs. Planet Analog is proud to present all the tutorial essays and graphics collected for that issue - starting with this outstanding analysis of voltage requirements by Fairchild's Ren Rossetti.
OC-48 SONET receiver consumes significantly less logic in FPGA News & Analysis 7/1/2002 Post a comment n many Sonet processing applications, a commercial vendor application-specific IC (ASIC) or application-specific standard product (ASSP) implements basic Sonet functions such as framing and performance monitoring. Frequently, a field-programmable gate array (FPGA) is also required to interface to the ASIC and perform customer-specific functions.
FPGAs adapt security functions in security blade design News & Analysis 7/1/2002 Post a comment s networking makes greater strides, the need for security becomes increasingly paramount. However, even with rapid advances in networking technology, security lags behind and in most instances, is only assigned to virtual private networks (VPNs) and firewalls.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.