Memory tester targets multi-chip packages Product News 10/30/2007 Post a comment The T5781 test system from Advantest offers high test speeds of 533-Mbits/s for next-generation MCPs, devices that combine multiple memory types, including NAND, NOR and DRAM, in a single package.
Google expands its venture-funding role in India Product News 10/29/2007 Post a comment Search giant Google Inc., describing the Indian market as hamstrung by a dearth of early-stage venture capital, announced two more pacts here that aim to give it more breadth in the venture funding of companies in the country.
Strong growth seen in September chip sales News & Analysis 10/29/2007 Post a comment Global chip sales surged by 5 percent in September, to $22.6 billion from the $21.5 billion recorded in August, the fastest increase so far this year, following an excellent August, according to figures from the World Semiconductor Trade Statistics (WSTS) organization.
Synopsys boosts manufacturing test quality Product News 10/26/2007 Post a comment Aimed at design organizations worldwide, the TetraMAX small delay defect automatic test pattern generator (ATPG) from Synopsys is designed to improve manufacturing test quality compared with conventional at-speed test methods.
Ultrawideband under the gun Product News 10/25/2007 Post a comment In the race to a gigabit-per-second wireless link for the digital home, some ultrawideband backers are gasping for air while Wi-Fi proponents are revving up for the next lap.
ST takes fresh approach to MCU evaluation Product News 10/25/2007 Post a comment ST has developed a self-contained, pre-programmed evaluation package for the recently-announced STM32 flash microcontroller family that provides both a fun introduction and serious development tools and links to an on-line development community.
TI fellow defines conditions and requirements for adaptive test at ITC News & Analysis 10/24/2007 Post a comment In his address at the International Test Conference in Santa Clara, Calif., Ken Butler, TI fellow at Texas Instruments, said growth in portable applications calls for the adoption of adaptive test, and that these changes in test strategies require corresponding modifications to design-for-test (DFT) tools and automatic test equipment (ATE).
FPGA debugger works at full speed Product News 10/24/2007 Post a comment EDA startup EDAptability has announced the availability of its FPGA and ASIC debugging tool TotalScope. With a combination of RTL level elaboration, model extraction and modification techniques with simulation, the tool offers unrivaled signal visibility, the company claims.
Researchers propose new design technique News & Analysis 10/23/2007 Post a comment Researchers from the Indian Institute of Technology together with another institute in Kolkata have proposed a layout-aware, coverage-driven technique for Illinois Scan Architecture used to cut test application time and test data volume in high-density circuits.
Japan wants more foreign investors News & Analysis 10/19/2007 Post a comment In order to maintain an economic and technology leadership position, it's imperative to be aware and mindful of trends, developments and events shaping the global market. Silicon Valley is no longer the center of the universe. To that end, EE Times vice president and editorial director Richard Wallace recently conducted an email interview with Tadashi Izawa, the incoming president of JETRO (Japan External Trade Organization).
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.