Buffers minimize jitter in clock distribution, differential signal lines News & Analysis 10/30/2002 Post a comment This article - an expanded version of a contribution on High Speed Design which appeared in EE Times' October 7th InFocus Signals section - discusses two different techniques for minimizing jitter: One uses buffering on clock distribution trees; the other uses buffers at each side of a differential signaling line. Cypress engineers explain.
Disciplined Power Management in Backplanes News & Analysis 10/30/2002 Post a comment GTLP-Gunning Transceiver Logic Plus-requires specialized voltage levels, and produces a number of static and dynamic states. It is important to understand how various power supply configurations affect efficiency and parts count. It is possible to adjust the levels of these power supplies, but the designer must recognize the impact on device performance. Fairchild's Eddie Suckow analyzes some of the tradeoff decisions effecting backplane system performance.
Choosing the Right Mixed-Signal Test Equipment News & Analysis 10/30/2002 Post a comment Today's high-speed, mixed-signal measurements challenge the capabilities of traditional test equipment. Agilent's Dave Sontag describes three different mixed-signal analysis solutions that provide time-correlated views of both analog and digital data, along with the strengths and weaknesses of each one.
Digital multiphase pumps power for CPU cores News & Analysis 10/29/2002 Post a comment While processor core voltages will drop to 1 V and below, current demand will rise, likely topping 150A by 2005, writes these power management engineers. New-generation PC power modules will need to process transients estimated to be 1000 A/ns at the processor, they say. The only way to do this is to stick fingers into the CPU, and anticipate what it needs - a technique they call "digital power." PA offers an early (albeit partial) exposure to what this entails.
Advanced switching boosts PCI Express News & Analysis 10/28/2002 Post a comment Data communications and telecommunications systems are converging, placing new requirements on the system building blocks that are at the heart of the communications infrastructure.
On a mission News & Analysis 10/24/2002 Post a comment Twenty years ago, it was an innovation with unrealized potential and a handful of advocates. Today, DSP serves innumerable applications and exerts a gravitational field that has drawn hundreds of silicon IP and software developers into its orbit.
Broadband FH Wireless Radios Solve Last-Mile Gap News & Analysis 10/24/2002 Post a comment Designers developing 2.4 GHz fixed broadband wireless radios must contend with interference from WLANs, microwave ovens, and more. By moving to a FH radio, designers can dodge this interference and provide high-speed Internet links.
Challenges in HyperTransport Verification News & Analysis 10/22/2002 Post a comment As HyperTransport designs proliferate the comm sector, verification will become a bigger issue for equipment and chip designers. Through a solid bus functional model, designers can tackle many of these verification headaches
SoCs no panacea for comms infrastructure News & Analysis 10/18/2002 Post a comment Like "military intelligence," the "comms infrastructure system-on-chip" is almost, but not quite, an oxymoron. Unlike battery-powered handsets, the room-size cellular basestations and telecom switching stations that make up the real comms infrastructure have scant need for highly integrated, small-form-factor, low-power ICs.
When Growth Recedes News & Analysis 10/17/2002 Post a comment Just a few short months ago, the connector industry was heartened by signs of growth, leading some manufacturers to believe they might yet salvage something from what otherwise has been a dismal 2002.