Rambus outlines memory roadmap to keep up with DDR SDRAM News & Analysis 6/12/2001 Post a comment TOKYO -- In a move to keep up with competitive memory technologies, Rambus Inc. late today outlined its future roadmap, including plans to boost the bandwidth of its RDRAM architecture by five-fold in 2005.
At the Rambus Developer Forum in Japan today, Rambus outlined its strategy in order to keep up with competitive next-generation memory technologies, most notably double-data-rate (DDR) SDRAM.
Network processor aims at adjunct role News & Analysis 6/12/2001 Post a comment Clearwater Networks (formerly XStream Logic) has developed a network processor that can work on its own but is intended to act as an adjunct, delving into layer-four to layer-seven frames at OC-192 (10Gbit/s) speeds.
Graphics processor reworked for 40Gbit/s comms News & Analysis 6/12/2001 Post a comment ClearSpeed Technology will reveal at Embedded Processor Forum this week (14 June) how it has modified an architecture originally designed for 3D graphics processing to handle network packet processing at 40Gbit/s.
16bit micro pulls in DSP engine News & Analysis 6/12/2001 Post a comment Although it was not at Embedded Processor Forum, Microchip Technology has unveiled the architecture that it plans to use in a new generation of microcontroller-DSP combos.
Embedded Processor Forum news News & Analysis 6/12/2001 Post a comment At Embedded Processor Forum this week (12-14 June), companies are lining up to disclose the architectures, cores and silicon they have developed.
Network processor field gaining new players News & Analysis 6/12/2001 Post a comment ATLANTA -- The crowded network processor scene is gaining new entrants promising previously unavailable levels of programmability for the high end of the market.
At SuperComm 2001 here last week, Xelerated Packet Devices AB provided the first details of its Packet Instruction Set Computer architecture, while at the Embedded Processor Forum this week in San Jose, Cognigine Corp. will unveil its Variable Instruction Set Communications architecture.
LSI, partners dial programmable core into ASICs News & Analysis 6/11/2001 Post a comment LSI Logic Corp. backed up two years of talk Monday (June 11) by rolling out details of a reconfigurable programmable logic function in an ASIC with partners Adaptive Silicon Inc. (ASi; Los Gatos, Calif.) and Ericsson.
MIPS Technologies offers 'soft' 64-bit core with floating-point unit News & Analysis 6/11/2001 Post a comment SAN JOSE -- During the Embedded Processor Forum here today, MIPS Technologies Inc. announced a synthesizable 64-bit processor core with integrated floating-point unit. The company said the 5Kf core is the industry's only synthesizable 64-bit processor with integrated FPU that's available for licensing.
Stanford Microdevices agrees to change name News & Analysis 6/11/2001 Post a comment Stanford University and Stanford Microdevices, Sunnyvale, Calif., said they have resolved their differences over the infringement case pending in theUnited States District Court for the Northern District of California.
Tensilica environment will handle multiple CPU cores News & Analysis 6/11/2001 Post a comment In an effort to ease the burden on engineers designing multiple-processor chips, Tensilica Inc. is readying a design environment that packs system-modeling tools, a shared-memory interface and enhanced debug capabilities for its Xtensa reconfigurable processor.
Analog Devices introduces first DSPs developed with Intel News & Analysis 6/11/2001 Post a comment NORWOOD, Mass. -- Analog Devices Inc. today formally announced its new Blackfin series of 16-bit digital signal processors (DSPs), the first product family to integrate the Micro Signal Architecture jointly developed by the Norwood-based company and Intel Corp.
Hynix adds picoTurbo RISC cores to ASIC, foundry offering News & Analysis 6/11/2001 Post a comment MILPITAS, Calif.--South Korea's Hynix Semiconductor Inc. has licensed two synthesizable RISC microprocessor cores from picoTurbo Inc. here for system-on-chip designs and ASICs aimed at cellular phones, MP3 players, smart cards, set-top boxes, modems, and other high-volume system applications.
ARC recodes for denser instructions News & Analysis 6/11/2001 Post a comment ARC International has developed a more compact instruction set for the next generation of its 32bit configurable processor to let it improve code density to the level offered by compressed formats such as the ARM Thumb and MIPS16.
Core changes allow reductions News & Analysis 6/11/2001 Post a comment MIPS Technologies has made major changes to the synthesisable HDL code for a new version of its 32bit processor core to reduce power consumption and code density.
Analog plans a path to 1GHz DSP News & Analysis 6/11/2001 Post a comment Analog Devices has launched the first implementation of the DSP architecture that it co-developed with Intel, and the company reckons it can produce versions that will run at 1GHz and above.
TI president doubts predictions of cellular resurgence News & Analysis 6/11/2001 Post a comment Some analysts have been raising their estimates for total cellular handset shipments in anticipation of a second-half resurgence in demand, but Tom Engibous, president, chief executive, and chairman of Texas Instruments Inc., the largest supplier of ICs to the market, said he has yet to see any
NEC soups up 64-bit MIPS core to break bottlenecks at higher frequencies News & Analysis 6/11/2001 Post a comment SANTA CLARA, Calif. -- NEC Corp.'s microprocessor operation here today announced major enhancements to its embedded 64-bit RISC processor platform, adding a deeper pipeline architecture and out-of-order execution capabilities. The enhancements will enable the 64-bit processors to deliver up to 1,600 million instructions per second (MIPS), while operating at speeds up to 800 MHz in the next couple years, said the company.
LSI adds fab capacity News & Analysis 6/11/2001 Post a comment LSI Logic will put up to 30% of its production through foundries following April's deal with Taiwan Semiconductor Manufacturing.
Software switches code on-the-fly News & Analysis 6/11/2001 Post a comment A spin-off from Manchester University claims to have crafted software that takes binary code prepared for one type of processor and, on-the-fly, translates it into the code required by another.
No speedy end to downturn News & Analysis 6/11/2001 Post a comment The UK's largest institutional investor has warned that the high-technology sector should expect a sluggish exit from the downturn.
ISSI expects loss for this quarter News & Analysis 6/8/2001 Post a comment Integrated Silicon Solution, Inc., Santa Clara, Calif. today announced that revenue and earnings for the June quarter will be approximately $20 million to $22 million with a net
loss of $3.5 million to $4 million, or approximately 14 cents per share.
RF Micro Devices to foundry Stanford's chips News & Analysis 6/8/2001 Post a comment Stanford Microdevices today announced a foundry agreement whereby SMDI's radio-frequency integrated circuits (RFICs) will be manufactured in RF Micro Devices' 4-inch gallium-arsenide (GaAs) heterojunction bipolar transistor (HBT) fabrication facility, located in Greensboro, N.C.
ISSI warns sales will drop 60% from prior quarter News & Analysis 6/8/2001 Post a comment SANTA CLARA, Calif. --Integrated Silicon Solution Inc. here today became the latest chip company to cut its forecast as sales continue to drop in the downturn. ISSI said it now expects revenues to sequentially plunge about 60% to the $20-to-$22 million range in the current quarter, compared to $52 million in the prior three-month period.
Speedy chips but no shrink News & Analysis 6/8/2001 Post a comment IBM has developed a silicon manufacturing technique that could lead to chips that are 35 per cent faster but which do not require any shrink in transistor size.
DDR and SDR share slots News & Analysis 6/8/2001 Post a comment STMicroelectronics has developed a single-chip termination network that lets PC motherboard builders use the same slots for 266MHz double data rate and existing 100MHz or 133MHz single data rate memories.
Cypress downgrades News & Analysis 6/8/2001 Post a comment Downgrades continued last week, in what marks the fifth month of companies reducing their revenue forecasts.
Lattice expects 30% sequential drop in sales due to PLD weakness News & Analysis 6/7/2001 Post a comment HILLSBORO, Ore.--Lattice Semiconductor Corp. today said it now expects revenues to fall 30% in the current fiscal quarter from $111.1 million in the prior three-month period. The company's management blamed the shortfall on a decline in programmable logic consumption within communications and computing markets.
Intel says quarter remains within earlier forecast News & Analysis 6/7/2001 Post a comment Intel said it expects that revenue, gross margin percentage and expenses for the second quarter will be within the previous expectations and slightly below the midpoint of the ranges provided on April 17. Intel still expects a seasonally stronger second half, it added.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.