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posted in October 2002
Buffers minimize jitter in clock distribution, differential signal lines
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10/30/2002   Post a comment
This article - an expanded version of a contribution on High Speed Design which appeared in EE Times' October 7th InFocus Signals section - discusses two different techniques for minimizing jitter: One uses buffering on clock distribution trees; the other uses buffers at each side of a differential signaling line. Cypress engineers explain.
Disciplined Power Management in Backplanes
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10/30/2002   Post a comment
GTLP-Gunning Transceiver Logic Plus-requires specialized voltage levels, and produces a number of static and dynamic states. It is important to understand how various power supply configurations affect efficiency and parts count. It is possible to adjust the levels of these power supplies, but the designer must recognize the impact on device performance. Fairchild's Eddie Suckow analyzes some of the tradeoff decisions effecting backplane system performance.
Digital multiphase pumps power for CPU cores
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10/29/2002   Post a comment
While processor core voltages will drop to 1 V and below, current demand will rise, likely topping 150A by 2005, writes these power management engineers. New-generation PC power modules will need to process transients estimated to be 1000 A/ns at the processor, they say. The only way to do this is to stick fingers into the CPU, and anticipate what it needs - a technique they call "digital power." PA offers an early (albeit partial) exposure to what this entails.
Signal integrity modeling tools critical to high speed IC package design
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10/16/2002   Post a comment
We would have liked to have this one for the EE Times' August 25th issue on IC package design -- especially since Ansoft's talent for extracting electrical RC equivalents from 3D mesh structures has catapulted it into one of the "Top Ten" slots among EDA tool vendors. As this tutorial shows, the RCs extracted from leadframes (and other package geometries) can be pumped into Spice to reveal an interesting picture of how a device package will perform under the stress of high-speed signals.
Data interface key to future apps
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10/16/2002   Post a comment
By the year 2005, applications such as games, high-end graphics, and routers will require chip-to-chip speeds of 10 to 100 GBytes/s, while IC I/O-related cost and power consumption must remain roughly at the levels we see today, writes this Rambus product planner. He says a new interface is needed and - guess what - it uses differential signaling. Check out this is a graphically-expanded version of an October 7th EE Times' feature...
Shutdown feature simplifies polarity selection
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10/16/2002   Post a comment
Linear Technology's Glen Brisebois returns with some pointers on reversing the polarity of an ac signal. (A Design Note from September's Planet Analog magazine.)
Standards are key to optimizing high-speed data bus communications
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10/7/2002   Post a comment
There are several options for high-speed data transmission, including wired solutions, optical fiber, and wireless. In this outstanding tutorial - only part of which appeared in EE Times' October 7th Signals Section - a TI thoroughly examines the tradeoffs for each option, including cost, data rate, and noise immunity. Though the emphasis is on wired applications, Clark Kinnaird looks a Electrical standards, Signaling rates, termination issues, driver pulse shaping and receiver responses. The co
Designers weigh in on the 6.25-Gbit/s move
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10/7/2002   Post a comment
While "gigahertz processors" are using 400-MHz external clocks with internal multipliers to obtain 1.2- or 1.6-GHz clock rates, that doesn't mean system designers aren't experiencing problems with data pumping.
Low Voltage Differential Signaling gives A/D converters higher sample rates.
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10/2/2002   Post a comment
A high-speed serial interface improves the sampling rate for wideband A/D converters. Among the articles targeted for exposure in EE Times' October 7th Signals Section on "High Speed" design, this piece shows how differential signaling can insure signal integrity for data sampled at 210-MHz clock rates.
Eye Opening Enhancements extend the reach of high-speed Interfaces
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10/2/2002   Post a comment
Typically the faster you go, the shorter you go, writes John Goldie, National Semiconductor's frequently-quoted applications guru. Data rate is inversely proportional to cable length. However analog interface techniques like pre-emphasis and equalization provide "eye opening" enhancements to extend the reach of the interconnect. New signal conditioning techniques optimize the signal quality at the receive end. This piece shows how.
Transmit or receive: The front end of broadband is analog
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10/2/2002   Post a comment
Cable modem, DSL and fixed wireless are the primary technologies driving new broadband applications and services in the home. While each technology utilizes a different medium for data delivery, all have one important thing in common: They utilize analog bandwidth. In this Planet Analog exclusive, TI engineers examine and compare the front ends three different broadband access systems. Parts Search

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What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.

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