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posted in July 2002
ICS posts fiscal 4Q gains, but down year-over-year
News & Analysis  
7/30/2002   Post a comment
Integrated Circuit Systems today reported it increased its profits by cutting costs and migrating to higher margin digital consumer products.
Tracking power supply makes split rails from single line
News & Analysis  
7/24/2002   Post a comment
This Maxim circuit generates the bipolar voltages required in many industrial analog applications, as well as contrast-control voltages for an LCD.
Rendering hair and fur needs computer graphics muscle
News & Analysis  
7/24/2002   Post a comment
Before they became a checklist item for SoC designs, RAMDACs would convert digital RGB values to a value that lit a CRT phosphor dot - and the rendering engine came up with each RGB value was equivalent to a time-share on a Cray supercomputer. The times have changed, says this computer graphics authority, all the work is done by a single chip - cheap enough to power a kid's gaming machine. Here's how it works. . . using hair and fur as an example.
It's not just 50 ohms: Some termination tips for differential and single-ended amplifiers
Blog  
7/24/2002   Post a comment
Most designers know that it is necessary to terminate a high-speed circuit to avoid reflection. Termination has been applied to digital, communication, RF, and analog circuits for decades. It is easy to place a 50 ohm resistor on an input and think that the job is done. The errors produced by incorrect understanding of termination are subtle and may go unnoticed. The designer may compensate for them by "tweaking" the circuit, when only a little forethought will yield the correct response from th
Eye scan saves time with multi-channel signal-integrity measurements
News & Analysis  
7/11/2002   Post a comment
An eye scan mode enhances the functionality of a logic analyzer, making it behave like analog oscilloscope. This capability brings an interesting new design and verification tool to developers of high-speed multiple-bus designs. Aligent's Art Porter shows how.
Real data cuts timing mumbo-jumbo for cascaded PLL designs
News & Analysis  
7/10/2002   Post a comment
PLLs provide the designer with the luxury of re-timing late or early clocks, eliminating the propagation delays that occur when clocks are transported over long distances. But typically there is noise and degradation - jitter - with each PLL in the chain, says this Cypress clocking expert. Here is an excellent example of timing budget measurements that can reduce the impact of noise in your system.
Satisfying cell phone-PDA combo devices' need for multiple voltages
News & Analysis  
7/8/2002   Post a comment
EE Times did not have room to print all the material we collected for its July 8th power management section - a contributed article package devoted to the engineering issues associated with extending battery life in merged cell phones and PDAs. Planet Analog is proud to present all the tutorial essays and graphics collected for that issue - starting with this outstanding analysis of voltage requirements by Fairchild's Ren Rossetti.


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