Breaking News
Content tagged with FPGA/PLD/CPLD
posted in January 2007
MathStar expands sales and support in Europe, Middle East, and Africa
News & Analysis  
1/31/2007   Post a comment
Arrix family of field programmable object arrays (FPOAs) now available to the Europe, Middle East, and Africa (EMEA) markets.
How to use programmable analog to measure MEMS gyroscopes
Design How-To  
1/31/2007   Post a comment
This article provides a methodology for designing MEMS gyroscope and similar systems using reprogrammable mixed-signal microcontrollers.
Altera's FPGAs are first to demonstrate support for PCI Express 2.0
News & Analysis  
1/31/2007   Post a comment
See demonstrations of Altera, PLDA, and Molex solutions for PCI-SIG's newly announced 5-GT/s PCIe 2.0 standard at DesignCon
Actel expands channel in China
News & Analysis  
1/30/2007   Post a comment
To promote wider use of its field-programmable gate array devices by Chinese designers, Actel Corp. announced a significant expansion of its sales channel in Greater China.
Enhanced Xilinx FPGA tool extends serial I/O debug capabilities
Product News  
1/30/2007   Post a comment
Check out Xilinx's latest version of its ChipScope Pro software and Serial I/O toolkit. Version 9.1i extends serial I/O debug capabilities to support 65-nm Virtex-5LXT FPGAs. This release also delivers 60% faster clock speeds and comprehensive low-cost BERT capabilities for RocketIO multi-gigabit transceivers.
Altera FPGAs address design challenges at DesignCon 2007
News & Analysis  
1/25/2007   Post a comment
High-end FPGAs, structured ASICs, and design tools as well as protocol solutions from Altera and its partners will be on exhibit at DesignCon 2007.
Xilinx at DesignCon 2007 (keynote and more)
News & Analysis  
1/25/2007   Post a comment
Xilinx Chairman, President, and CEO Wim Roelandts to deliver keynote address.
How to design 65nm FPGA DDR2 memory interfaces for signal integrity
Design How-To  
1/24/2007   Post a comment
Practical techniques for "correctness by design" in DDR2 interfaces, from a signal integrity (SI) perspective; follow these guidelines to make your next 65nm FPGA design a success.
Virtex-4 FX development platform speeds embedded system design
Product News  
1/24/2007   Post a comment
Xilinx Inc. announced immediate availability of its lead-free, RoHS compliant ML410 development platform based on its Virtex-4 FX60 FPGA.
Lattice announces new FreedomChip seamless cost reduction path for LatticeSC/M FPGAs
Product News  
1/23/2007   Post a comment
FreedomChip from Lattice provides better than 99% fault coverage for customer specific designs with 100% timing compatibility.
Multiple LatticeSC/M FPGA devices released to volume production
Product News  
1/23/2007   Post a comment
Lattice announce that production quantities of its LatticeSC/M FPGA devices are available less than one year from their introduction.
Mouser Electronics and Actel enter into global distribution agreement
News & Analysis  
1/23/2007   Post a comment
Mouser Electronics and Actel extend global availability of Actel's innovative non-volatile single-chip FPGAs.
Xilinx Virtex-5 FPGAs and PlanAhead software honored for design innovation
News & Analysis  
1/23/2007   Post a comment
Industry's first 65nm FPGAs and design planning and analysis tool finalists in prestigious industry awards.
How to achieve software load-balance by using a message-based interconnect protocol
Design How-To  
1/22/2007   Post a comment
A message-based host-peripheral interconnect strategy will be crucial in the design of Next-Gen wire-speed storage, telecommunication, and networking systems.
MathStar and Mouser enter into distribution agreement
News & Analysis  
1/18/2007   Post a comment
MathStar/Mouser partnership unites the world's fastest programmable logic devices with the world's fastest-growing catalog distributor in the electronics industry.
How to Choose the Right FPGA
Design How-To  
1/18/2007   Post a comment
This article analyzes the features and tradeoffs of the latest Xilinx FPGAs with regards to performance, power consumption, signal integrity, serial fabrics, memory, and speed.
Small form factor FPGA packaging for space/power-constrained handheld electronics
Product News  
1/17/2007   Post a comment
Ultra low-power PolarPro and Eclipse II FGPAs from QuickLogic are now available in 6x6 mm and 8x8 mm packages with up to 196 balls.
LatticeECP2M FPGA named DesignVision awards finalist
News & Analysis  
1/17/2007   Post a comment
Lattice's SERDES-supporting low-cost FPGA family continues to collect industry accolades.
PolarPro, Eclipse II FPGAs housed in ultra-small packages
Product News  
1/17/2007   Post a comment
To meet the small-form factor needs of the handheld electronics sector, QuickLogic Corp. has started to house FPGAs in its PolarPro and Eclipse II product families in 6x6 mm and 8x8 mm packages.
Libero IDE 7.3 improves design flow for Actel FPGAs
Product News  
1/17/2007   Post a comment
Actel's latest version of its Libero IDE now offers full support for its low-power, flash-based IGLOO family of FPGAs.
Barco Silex presents JPEG2000 encoder core optimized for digital cinema and broadcasting
Product News  
1/16/2007   Post a comment
New JPEC2000 IP core from Barco Silex targets single-chip FPGAs or ASICs for use in digital cinema and broadcasting applications.
Synaptics announces configurable Synaptics OneTouch solution
Product News  
1/16/2007   Post a comment
Synaptics OneTouch configurable capacitive sensing solution allows customers to develop customized interfaces from concept through mass production.
HP claims FPGA breakthrough
News & Analysis  
1/16/2007   Post a comment
Hewlett-Packard Co. claimed a breakthrough that could lead to the creation of field programmable gate arrays (FPGAs) up to eight times denser — while using less energy for a given computation — than those currently being produced today.
One-button MATLAB-to-C conversion
Design How-To  
1/16/2007   10 comments
In the past, converting MATLAB algorithms into C code required manual translation--a slow, error-prone process. Now, you can generate C automatically using Catalytic MCS. Here's how it works.
Reduce power consumption in embedded designs with dynamic voltage and frequency scaling
Design How-To  
1/16/2007   Post a comment
To reduce power consumption, processors, developers who use support dynamic voltage and frequency scaling (DVFS) will find it a useful in a wide range of mobile and embedded designs.
Video and image processing design using FPGAs
Design How-To  
1/12/2007   Post a comment
FPGAs eliminate the up-front non-recurring engineering costs and minimum order quantities associated with ASICs, and the costly risks of multiple silicon iterations through the capability to be reprogrammed as needed during the design process.
FPGAs vs. DSPs: A look at the unanswered questions
Design How-To  
1/11/2007   Post a comment
BDTI looks at the open questions about FPGAs' performance, cost, power, and ease of development. It also explains why FPGAs might benefit from the move to deep-submicron processes.
Chip surplus swells in 4Q as market cools
News & Analysis  
1/10/2007   Post a comment
Amid signs of a seasonal slowdown in the semiconductor market, excess chip inventories continued to swell in the fourth quarter of 2006, leaving the industry with a surplus of parts worth $4.3 billion, according to iSuppli Corp. (El Segundo, Calif.)
SANYO adopts Altera's HardCopy structured ASIC for award-winning home theater projector
News & Analysis  
1/9/2007   Post a comment
Using Altera's Structured ASIC approach allows SANYO to perform rapid component revisions for market-leading picture quality.
Why Multiprocessor DSP Systems Need CORBA
Design How-To  
1/9/2007   Post a comment
CORBA enables software components in a multiprocessor system to easily communicate--regardless of what language they are written in, what OS they run on, or where they are located. Even better, CORBA makes it easy to move functionality between DSPs, GPPs, and FPGAs.
The Top-10 Programmable Logic "How To" articles of 2006
Design How-To  
1/5/2007   Post a comment
From alternative FPGA architectures to implementing three inversions using only two NOT gates (and no XOR gates), here's the "best-of-the-best" from 2006.
Updated ispLEVER tool suite supports SerDes-based FPGAs
Product News  
1/4/2007   Post a comment
Lattice Semiconductor has released the latest ispLEVER design tool suite update, version 6.1 Service Pack 1, which includes support for Lattice's ECP2M20 FPGAs and 32-bit embedded processor ports to LatticeSC/M and LatticeXP families.
Tutorial: Linear Feedback Shift Registers (LFSRs) - Part 3
Design How-To  
1/4/2007   Post a comment
In which we discover how LFSRs can be of use in encryption and decryption, cyclic redundancy check (CRC), data compression, and a myriad other applications.


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41 comments
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18 comments
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Glen Chenier
12 comments
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45 comments
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