Programmable PCIe solution costs less than $13 in volume Product News 10/27/2005 Post a comment For less than $13 in volume, Lattice Semiconductor Corp. is offering a programmable PCI Express (PCIe) solution that combines its LatticeECP and LatticeEC field programmable gate arrays (FPGAs) with the Genesys Logic GL9711 PCIe PHY, and Northwest Logic’s PCIe IP core.
Altera, Wi-LAN to partner on WiMAX modems News & Analysis 10/26/2005 Post a comment FPGA supplier Altera Corp. has formed a partnership with Canadian broadband wireless technology provider Wi-LAN Inc. to deliver a programmable, low-cost WiMAX-compliant base transceiver station (BTS) modem solution supporting the IEEE 802.16-2004 standard.
H.264 video encoding with Stretch's S5000 software-configurable processor Design How-To 10/24/2005 Post a comment From a technical perspective, the primary difference between H.264 and other MPEG standards is the use of multiple reference frames, wider search ranges, and smaller macro blocks for motion estimation, all of which ultimately translate to increased computational intensiveness. A Stretch engineer explains how the new S5000 software-configurable processor offers unusual scalability and flexibility.
Cypress posts another loss News & Analysis 10/20/2005 Post a comment Semiconductor supplier Cypress Semiconductor Corp. reported a GAAP net loss of $5.9 million, or 4 cents per share on sales of $227.1 million in the third quarter, compared to earnings of $4.3 million, or 12 cents per share on sales of $219.6 million in the year-ago quarter.
Routing density analysis of ASICs, Structured ASICs, and FPGAs Design How-To 10/19/2005 Post a comment This article uses well-known routing estimation techniques to analyze the trends of routing area requirements for standard cell ASICs, coarse-grained standard metal Structured ASICs, and field programmable gate arrays FPGAs. The cell granularity and the metal interconnect structure of these diametrically different architectures is analyzed and compared.
Structured ASICs are cool! Programmable Logic DesignLine Blog 10/17/2005 Post a comment In addition to CPLDs, FPGAs, FPAAs, FPNAs, and programmable processors, Programmable Logic Designline is also going to cover Structured ASICs.
Microchip’s DSP PICs: Whatever next? Programmable Logic DesignLine Blog 10/14/2005 Post a comment You can only imagine my surprise to hear that those clever little rapscallions at Microchip are now selling 16-bit PIC microcontrollers with DSP-centric functionality!
Who is that masked man? Programmable Logic DesignLine Blog 10/12/2005 Post a comment I’m currently bouncing off the walls with excitement, because this is my first day to officially take the reins as the editor of this mega-cool site.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments