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Content tagged with FPGA/PLD/CPLD
posted in November 2001
Lattice prepares to enter FPGA fray
News & Analysis  
11/29/2001   Post a comment
Altera Corp. and Xilinx Inc. may soon be looking over their shoulders at Lattice Semiconductor Corp., which is planning to join the FPGA fray sometime next year. The company's newly appointed president Steven Laub called FPGAs "a natural extension for us, both customerwise and technologywise."
Atmel says logic conversion blocks cut costs compared to FPGAs and CPLDs
News & Analysis  
11/21/2001   Post a comment
NANTES, France--Atmel Corp. here today announced new 0.25- and 0.35-micron embedded memory blocks for its Ultimate Logic Conversion products, which will enable users of field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) to move their designs to lower cost ULC-configured devices.
Altera, Synopsys plan 'ASIC-like' design solutions for complex PLDs
News & Analysis  
11/14/2001   Post a comment
SAN JOSE -- Altera Corp. and Synopsys Inc. today announced plans to jointly develop ASIC-like design solutions for complex system-on-programmable-chip (SoPC) devices. The partnership will address the need for next-generation design and verification flows for high-density programmable logic devices, said the two companies.
Nanoscale transistor circuits move into logic
News & Analysis  
11/9/2001   Post a comment
Nanotechnology continues its rapid evolution as two more research groups report on the assembly of individual molecules and molecular scale structures into functional logic circuits.
Clear Logic awarded FPGA-to-ASIC conversion patent
News & Analysis  
11/8/2001   Post a comment
Clear Logic Inc. may be turning the legal tables on Altera Corp. The tiny San Jose company, which is being sued by Altera for alleged illegal use of its mask technology in performing FPGA-to-ASIC conversions, today said it has been awarded a patent for the technique that may predate Altera's own conversion technology.
Mentor's first wave of new FPGA synthesis tools targets 50 million gate designs
News & Analysis  
11/6/2001   Post a comment
WILSONVILLE, Ore. -- Three months after disclosing an ambitious plan to redefine design software for field programmable gate arrays, Mentor Graphics Corp. here is preparing to ship its first beta versions of knowledge-based, heuristic synthesis tools targeting next-generation FPGAs with up to 50 million ASIC gates on a chip.
Cellular base station IC sales to regain momentum after 2002, says new report
News & Analysis  
11/5/2001   Post a comment
OYSTER BAY, N.Y.-- Integrated circuit revenues for cellular-phone base stations will remain relatively flat at around $380 million in the next year or so, but IC sales are expected to gain momentum after 2003, when carriers move to next-generation wireless services and increase the volume of their networks, according to a new forecast from Allied Business Intelligence Inc. here.


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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