DSP Meets FPGA: Is Massive Parallelism Enough? Design How-To 11/25/2003 Post a comment The wireless communications technology explosion came at a near-perfect time for FPGA companies with access to leading-edge fabrication technology. Reductions in FPGA feature size to 0.18 micron and below made more gates available as well as less expensive on a per-gate basis. Tighter geometries also gave significant performance boost. Lower operating voltages made the chips less power hungry. But is massive parallelism enough? Jack Shandle takes a look at the advantages and disadvantages of DSP
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.