Breaking News
Content tagged with FPGA/PLD/CPLD
posted in November 2005
Page 1 / 2   >   >>
Are we all in sync?
Programmable Logic DesignLine Blog  
11/30/2005   1 comment
How cool to hear that asynchronous logic design is becoming one of the better-kept secrets in the chip design community.
How to reduce costs by integrating PCI interface functions into CPLDs
Design How-To  
11/30/2005   Post a comment
Programmable logic-based PCI interface solutions offer significant advantages over ASSPs in terms of cost, board space reduction, flexibility, and obsolescence-proofing.
Platform modeling workshop
Design How-To  
11/29/2005   Post a comment
Forthcoming workshop to be held December 9, 2005 from 9:00 am to 6:00 pm at the Europole Hotel, Grenoble, France.
Design software provides improved performance for Lattice FPGAs
News & Analysis  
11/29/2005   Post a comment
Companies claim designers can expect to achieve up to a 20 percent performance improvement and significant area savings compared to competitive solutions.
Lattice and Synplicity CPLD/FPGA seminar series
News & Analysis  
11/29/2005   Post a comment
Forthcoming seminar series to be held in cities throughout the United States and in multiple cities in Europe and Asia.
Platform modeling workshop
Programmable Logic DesignLine Blog  
11/29/2005   Post a comment
If you're going to be in Grenoble, France on 9 December 2005 and have nothing to do, then I have just the place for you to go...
Design tool suite boosts FPGA-PCB integration
Product News  
11/29/2005   Post a comment
Altium releases Altium Designer 6.0, which provides a unified approach to electronic product development.
Synplicity tool claims improved performance for Lattice FPGAs
Product News  
11/29/2005   Post a comment
Lattice Semiconductor and Synplicity jointly that version 8.4 of Synplicity's Sinplify Pro logic synthesis engine provides additional performance enhancing features for Lattice FPGA devices, resulting in up to 20 percent performance improvement and significant area savings.
FPGAs accelerate automotive navigation product development
News & Analysis  
11/28/2005   Post a comment
Blaupunkt Shortens Development Time for its TravelPilot Rome Automotive Navigation System Using Altera's Cyclone FPGAs and Nios II Embedded Processors.
ARCHITECTURES: Designers quietly tap async practices
News & Analysis  
11/28/2005   Post a comment
Asynchronous logic design is becoming one of the better-kept secrets in the chip design community.
Happy Thanksgiving!
Programmable Logic DesignLine Blog  
11/23/2005   Post a comment
"Good Golly Miss Molly!" It can't be time for Thanksgiving again; I only just recovered from celebrating last year's holiday...
Power considerations in designing with 90 nm FPGAs
Design How-To  
11/23/2005   Post a comment
This "How To" article explores the various power considerations that can be addressed by the FPGA vendor and the end user.
Webinar: implementing packet processing protocols using FPGAs
Design How-To  
11/22/2005   Post a comment
Using FPGAs to build packet processing protocols using FPGAs with an embedded multi-core engine for software and hardware flexibility.
The dawn of age of materials science
Programmable Logic DesignLine Blog  
11/22/2005   Post a comment
A plethora of new announcements indicate that the 21st century will be known as "The Age of Materials Science."
Hand-cranked computers!
Programmable Logic DesignLine Blog  
11/18/2005   Post a comment
When I created a hand-cranked computer spoof in the days of yore, it seems that I was years ahead of my time!
Xilinx establish training network for Asia Pacific
News & Analysis  
11/18/2005   Post a comment
Eight partners operating 22 training locations in ten countries deliver FPGA design courses across the Asia Pacific region.
Xilinx offering design training in Asia through provider network
News & Analysis  
11/18/2005   Post a comment
Xilinx wants designers in Asia to hit the books on programmable logic design. The company has assembled a network of authorized training providers to help them do it.
Timing analysis tool expands FPGA and board design flows
Product News  
11/17/2005   Post a comment
Version 8.0 of Chronology's TimingDesigner has enhanced timing analysis and diagramming capabilities for FPGA and board design flows.
Commentary: Is Infineon going fabless?
News & Analysis  
11/17/2005   Post a comment
Infineon Technologies’ decision to split its DRAM and logic businesses and seek an IPO for its memory business could foreshadow the German chip maker's move to a fabless model for CMOS manufacturing below the 90-nm node.
Companies collaborate on debug software for Altera FPGAs
News & Analysis  
11/16/2005   Post a comment
Tektronix, Altera and First Silicon Solutions introduced FPGAView, a software package from FS2 for Tektronix TLA logic analyzers that the companies claim enables real-time debugging of Altera's field-programmable gate arrays.
Rave Computing joins Nallatech's channel partner program
News & Analysis  
11/16/2005   Post a comment
Rave to provide integration services expertise for Nallatech's FPGA-based systems.
eASIC selects Fujitsu as foundry supplier for 90nm Structured ASICs
News & Analysis  
11/16/2005   Post a comment
Fujitsu employs its in-house direct-write e-Beam technology to manufacture eASIC's maskless and NRE-free Structured ASICs with fast turnaround times.
ESL even I can understand!
Programmable Logic DesignLine Blog  
11/16/2005   Post a comment
In which we discover how to make tightly-managed architecture and micro-architecture changes safely and quickly
New 802.16d/e PHY and MAC IP Implemented Completely in C/C++
Design How-To  
11/16/2005   Post a comment
Based on Stretch Inc's software-configurable processor, Tata Elxsi's WiMAX IP offers flexibility and time-to-market advantages.
Performing rapid and safe evaluations at the architectural level
Design How-To  
11/16/2005   Post a comment
A new approach that gives designers the tools to tackle changes quickly and safely at the architectural level while staying close to the hardware implementation.
Logic cell architecture sharply lowers FPGA power consumption
Product News  
11/16/2005   Post a comment
QuickLogic Corp.'s experience with Eclipse II customers has led the company to develop a new FPGA line called PolarPro, which is designed with a new logic cell architecture that is tailored to address the needs of power-sensitive applications. PolarPro will give the battery-powered, handheld designers the option of choosing an FPGA, which hasn't been viable due to its high-cost and power-consuming nature.
Xilinx investing $40 million in Singapore operations
News & Analysis  
11/15/2005   Post a comment
Xilinx plans to invest $40 million to quadruple manufacturing capacity at the company's Asia Pacific headquarters in Singapore.
High-performance computing becomes interactive
Product News  
11/14/2005   Post a comment
New software platform brings ease and interactivity of desktop applications to high-performance computers.
Serial interconnect protocol optimized for Stratix II GX FPGAs
Product News  
11/14/2005   Post a comment
Second-generation serial protocol extends flexibility, increases performance, and offers cost savings.
High-performance computing become interactive
Product News  
11/14/2005   Post a comment
New software platform brings ease and interactivity of desktop applications to high-performance computers.
Valuable aid in managing designs
Programmable Logic DesignLine Blog  
11/11/2005   Post a comment
Perforce is an incredibly useful tool for managing the hardware and software portions of a design.
New platform accelerates design of data acquisition systems
Product News  
11/11/2005   Post a comment
New high-performance platform from National Semiconductor and Xilinx accelerates the design of gigahertz-speed data acquisition systems.
AccelChip DSP Synthesis with IP-Explorer technology
Product News  
11/10/2005   Post a comment
AccelChip to demonstrate its new IP Explorer technology and present a paper at forthcoming SDR conference.
Interesting papers and webcasts from TechOnLine
Design How-To  
11/10/2005   Post a comment
TechOnLine are featuring some interesting Programmable Logic and Structured ASIC-related papers and webcasts.
Altera net seminar on high-speed serial design using FPGAs
News & Analysis  
11/10/2005   Post a comment
In its forthcoming net seminar, Altera will describe how FPGAs can simplify high-speed serial design while maintaining low power and optimal signal integrity.
High-volume programming service for the world's smallest microcontroller
News & Analysis  
11/10/2005   Post a comment
Source Electronics provides high-volume programming service for Microchip's PIC10F – the world's smallest microcontroller.
FPGA maker delivers design flow for ARM7-based devices
Product News  
11/9/2005   Post a comment
Actel Corp.'s has upgraded its Libero Integrated Design Environment (IDE), providing a design flow that will enable designers to integrate CoreMP7, its recently introduced soft ARM7 family processor, into its field programmable gate arrays (FPGAs).
Low power FPGAs and the origin of the universe
Programmable Logic DesignLine Blog  
11/8/2005   Post a comment
QuickLogic introduce ultra-low-power FPGAs and Stephen Hawking presents a lecture on the origin of the universe.
Magma offering design flow for new ChipX structured ASICs
News & Analysis  
11/8/2005   Post a comment
Structured ASIC supplier ChipX and EDA vendor Magma Design Automation Inc. have made available an RTL-to-GDSII design flow to support the new CX6000 structured ASIC product line.
Altera qualifies MAX II CPLD family for extended temperature range
Product News  
11/8/2005   Post a comment
Low-cost CPLDs are now available to provide greater design flexibility for automotive, military, and industrial applications.
Altera delivers new simulation capability
Product News  
11/8/2005   Post a comment
With the release of its DSP Builder development tool version 5.1, Altera delivers new simulation capability.
QuickLogic introduces low power PolarPro FPGAs
Product News  
11/7/2005   Post a comment
New PolarPro FPGA architecture features embedded FIFO controllers and addresses power-sensitive applications by reducing inactive power consumption to less than 10uA.
Aldec releases Active-HDL 7.1
Product News  
11/7/2005   Post a comment
Latest release of FPGA and ASIC design entry and verification platform includes new simulation technology and SystemVerilog support.
Building an FPGA FIFO without using logic resources
Design How-To  
11/7/2005   Post a comment
This "How To" article describes how to build a full-featured FIFO in an FPGA without consuming valuable logic resources.
Programmable logic outpacing MPU industry, Altera exec claims
News & Analysis  
11/3/2005   Post a comment
Programmable logic developers are a decade ahead of the microprocessor industry, and use of the chip technology continues to rise, an Altera Corp. executive told a conference in India.
Hmmm, dual-port FPGA memories
Programmable Logic DesignLine Blog  
11/2/2005   Post a comment
There's more to implementing dual-port memories in FPGAs than one might think.
Dual-port FPGA memory blocks: the ultimate system interconnect solution?
Design How-To  
11/2/2005   Post a comment
The performance of dual-ports memory blocks in FPGAs is highly dependent on device utilization and how these blocks are instantiated.
Actel's new design flow for FPGAs with ARM7 core
Product News  
11/2/2005   Post a comment
Actel's Libero IDE delivers secure, comprehensive design flow for developinf FPGAs with ARM7 microprocessor core.
PLD tool suite gives more control to the designer
Product News  
11/2/2005   Post a comment
Lattice Semiconductor Corp. has released version 5.1 of its ispLEVER programmable logic design (PLD) tool suite, which it claims boosts field programmable gate array (FPGA) logic utilization by as much as 35% and design operating frequencies up to 25%.
MIL-STD-1553B IP core offers full code coverage
Product News  
11/2/2005   Post a comment
Core1553BRT version 3.0 IP core, the latest version of Actel Corp.'s MIL-STD-1553B remote terminal core, offers a higher level of redundancy by incorporating the use of protected state machines.
Page 1 / 2   >   >>


Flash Poll
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Rishabh N. Mahajani, High School Senior and Future Engineer

Future Engineers: Don’t 'Trip Up' on Your College Road Trip
Rishabh N. Mahajani, High School Senior and Future Engineer
2 comments
A future engineer shares his impressions of a recent tour of top schools and offers advice on making the most of the time-honored tradition of the college road trip.

Max Maxfield

Juggling a Cornucopia of Projects
Max Maxfield
7 comments
I feel like I'm juggling a lot of hobby projects at the moment. The problem is that I can't juggle. Actually, that's not strictly true -- I can juggle ten fine china dinner plates, but ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
37 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Karen Field

July Cartoon Caption Contest: Let's Talk Some Trash
Karen Field
139 comments
Steve Jobs allegedly got his start by dumpster diving with the Computer Club at Homestead High in the early 1970s.

Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)