Are we all in sync?
Programmable Logic DesignLine Blog 11/30/2005 1 comment
How cool to hear that asynchronous logic design is becoming one of the better-kept secrets in the chip design community.
Platform modeling workshop
Programmable Logic DesignLine Blog 11/29/2005 Post a comment
If you're going to be in Grenoble, France on 9 December 2005 and have nothing to do, then I have just the place for you to go...
Programmable Logic DesignLine Blog 11/23/2005 Post a comment
"Good Golly Miss Molly!" It can't be time for Thanksgiving again; I only just recovered from celebrating last year's holiday...
Programmable Logic DesignLine Blog 11/18/2005 Post a comment
When I created a hand-cranked computer spoof in the days of yore, it seems that I was years ahead of my time!
Commentary: Is Infineon going fabless?
News & Analysis 11/17/2005 Post a comment
Infineon Technologies’ decision to split its DRAM and logic businesses and seek an IPO for its memory business could foreshadow the German chip maker's move to a fabless model for CMOS manufacturing below the 90-nm node.
Logic cell architecture sharply lowers FPGA power consumption
Product News 11/16/2005 Post a comment
QuickLogic Corp.'s experience with Eclipse II customers has led the company to develop a new FPGA line called PolarPro, which is designed with a new logic cell architecture that is tailored to address the needs of power-sensitive applications. PolarPro will give the battery-powered, handheld designers the option of choosing an FPGA, which hasn't been viable due to its high-cost and power-consuming nature.
FPGA maker delivers design flow for ARM7-based devices
Product News 11/9/2005 Post a comment
Actel Corp.'s has upgraded its Libero Integrated Design Environment (IDE), providing a design flow that will enable designers to integrate CoreMP7, its recently introduced soft ARM7 family processor, into its field programmable gate arrays (FPGAs).
PLD tool suite gives more control to the designer
Product News 11/2/2005 Post a comment
Lattice Semiconductor Corp. has released version 5.1 of its ispLEVER programmable logic design (PLD) tool suite, which it claims boosts field programmable gate array (FPGA) logic utilization by as much as 35% and design operating frequencies up to 25%.