Awesome! Two amazing books for free! Blog 11/30/2010 14 comments Did you see my reviews of the books uC/OS-III The Real-Time Kernel by Jean Labrosse and uC/TCP-IP by Christian Légaré? Well, I just heard how you can get FREE copies of both these works…
Book Review: uC/TCP-IP by Christian Légaré Engineer’s Bookshelf 11/30/2010 2 comments I have to say that I am very, VERY impressed with the quality of books that are being written by the folks at Micriµm – the one I just finished reading on TCP-IP still has my head buzzing!
ESL, FPGAs, and configurability Blog 11/29/2010 1 comment Here’s a taxonomy for ESL and FPGAs that will hopefully prevent definitions from becoming as word- distorted and confused as they have become in so many other areas of EDA.
From RTL to GDSII in Just Six Weeks! Blog 11/29/2010 37 comments The amazing story of how one man single-handedly invented a new computing architecture, designed a multi-million-gate SoC, and went from RTL to GDSII tapeout in just six weeks.
IP in FPGAs: Blessing and a curse Blog 11/22/2010 12 comments With the IP-SoC 2010 event next week in Grenoble, we see FPGAs finally getting some kind of exposure. But, Dave Orecchio of GateRocket indicates that FPGA designers need to be aware of the unique nuances of using IP in these programmable platforms, and put in place tools and methodologies to overcome the IP use obstacles to success.
The Emperor of Ice-Cream Blog 11/16/2010 5 comments I just ran across a poem called The Emperor of Ice-Cream (it’s the author’s hyphen, not mine). If it hadn’t been explained to me I wouldn’t have a clue what it was about. Once you do know what it’s about, however, re-reading it really makes you think…
*Footprint Graphics* or *Land Patterns*? Blog 11/16/2010 9 comments OK, I know I’m supposed to spend my days pondering the imponderables pertaining to programmable logic, but FPGAs end up on circuit boards, and I just ran into a problem with regard to PCB terminology…
New Lattice MachX02 is the Do-It-All PLD Product News 11/8/2010 3 comments 65nm MachX02 PLDs deliver 3X increase in logic density, 10X increase in embedded memory, more than a 100X reduction in static power, 30% lower cost compared to their predecessors.
Having fun with programmable logic Blog 11/5/2010 1 comment You know how I often say ‘Have you done anything interesting recently with CPLDs or FPGAs or any other form of programmable logic? If so please tell me about it.’ Well someone did…
Eye movement controls gaming console News & Analysis 11/4/2010 11 comments A team of engineers inside National Instruments has unveiled the LabView source code to "EyeMario," which demonstrates how video gamers can use their eyes to control Nintendo gaming consoles.
Quickpath IP bound for Achronix FPGAs News & Analysis 11/4/2010 4 comments Achronix will be including a hard Quickpath IP core in support of processor communications on forthcoming field programmable gate arrays enabled by Intel manufacturing.
BEEcube's BEE4-W speeds prototyping of military/aerospace comm designs Product News 11/3/2010 Post a comment The BEE4-W is BEEcube's latest generation FPGA Berkeley Emulation Engine (BEE) platform, specifically designed to address rapid system-level prototyping of wireless and digital communications designs. It is a commercial, stackable full speed multi-FPGA based prototyping platform, integrated with DAC/ADC modules for mixed signal and digital communications designs. With four (4) integrated ADC and DAC solutions, the Xilinx Virtex-6 FPGA based BEE4-W enables a wide range of high-performance, real-t
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments