Embedded Systems Conference
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Content tagged with FPGA/PLD/CPLD
posted in December 2003
ASIC's and FPGA's benefit from IP Cores for Memory Interfacing
Product News  
12/24/2003   Post a comment
FPGA designers can now bolt on higher performance external memory more easily. Read on...
At the Core of It
Product News  
12/24/2003   Post a comment
Video over IP FPGA core collaborations. Can you see me now....
Moore Means More
Product News  
12/24/2003   Post a comment
New floorplanning architecture targets next generation domain based FPGA designs.
FPGA Configurator Memory IC Deals with Static
Product News  
12/24/2003   Post a comment
Boot your FPGA to different functions with this fast, dense, and small FPGA configurator IC.
Hierarchical Floorplanning and Analysis Software for High-Density FPGAs
Product News  
12/16/2003   Post a comment
This white paper from Hier Design discusses their vision and strategy for tackling very dense FPGA designs.
Antifuse-Based FPGAs at Extended Temperatures
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12/16/2003   Post a comment
Antifuse-Based FPGAs at Extended Temperatures
FPGA on 90nm Process with Dedicated DSP Functionality
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12/16/2003   Post a comment
FPGA on 90nm Process with Dedicated DSP Functionality
Programmable Logic-Based Local Interconnect Network (LIN)
Product News  
12/16/2003   Post a comment
Programmable Logic-Based Local Interconnect Network (LIN)
v3.1 Design Tools Ease Design Tasks
Product News  
12/16/2003   Post a comment
v3.1 Design Tools Ease Design Tasks
From Box To Box
Product News  
12/8/2003   Post a comment
From Box To Box
Luxury of Space
Product News  
12/8/2003   Post a comment
Luxury of Space
Xilinx set to debut novel FPGA architecture
News & Analysis  
12/8/2003   Post a comment
It's easier to embed ASIC blocks in an FPGA than the other way around, a fact that has allowed FPGA suppliers to span outside their traditional market into sockets previously addressable only by custom chips.
Design Security For Bluetooth Digital Gaming
Product News  
12/2/2003   Post a comment
Design Security For Bluetooth Digital Gaming
Rad-Hardened Family Of FPGAs
Product News  
12/2/2003   1 comment
Rad-Hardened Family Of FPGAs
First Self-Adjusting Automated Tray Feeder
Product News  
12/2/2003   Post a comment
First Self-Adjusting Automated Tray Feeder
"Bullet Proof" Solution to Intellectual Property Theft?
Product News  
12/2/2003   Post a comment
"Bullet Proof" Solution to Intellectual Property Theft?
Axcelerator Devices For Industrial Temp.
Product News  
12/2/2003   Post a comment
Axcelerator Devices For Industrial Temp.
Partners Program Simplifies Actel-Based Designs
Product News  
12/2/2003   Post a comment
Partners Program Simplifies Actel-Based Designs


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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