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Content tagged with FPGA/PLD/CPLD
posted in December 2005
Interesting whitepapers available from TechOnLine
Design How-To  
12/29/2005   Post a comment
Interesting items from TechOnLine's Technical Paper Library Highlights newsletter include testing interrupt priority levels and graph-based physical synthesis.
Just what is a Christmas Cracker?
Programmable Logic DesignLine Blog  
12/28/2005   Post a comment
Having been born in the UK, this is the time of year when I have to explain British holiday traditions to my American friends, such as "just what is a Christmas Cracker?"
Automotive gateways spearhead in-car network integration
Design How-To  
12/28/2005   Post a comment
Electronic gateways must provide bandwidth and latency in tying together diverse data buses. Here's what challenges design engineers face, and how to overcome them.
QuickLogic, Mentor in OEM agreement on FPGA tools
News & Analysis  
12/28/2005   Post a comment
QuickLogic customers will get access to Mentor Graphics' Precision Synthesis tool within the QuickLogic Quickworks FPGA development environment through an OEM agreement between the companies.
A practical approach to reusing HDL code in FPGA designs
Design How-To  
12/28/2005   Post a comment
Smart FPGA designers have realized that it is practical to recycle existing HDL code. This paper discusses how to reuse existing code that was not initially designed for reuse.
Happy Holidays (especially Boxing Day)!
Programmable Logic DesignLine Blog  
12/22/2005   Post a comment
Coming from the UK but now living in the USA, this is the time of year when I have to explain just what "Boxing Day" is all about.
Lattice settles shareholder suit
News & Analysis  
12/22/2005   Post a comment
Programmable logic supplier Lattice Semiconductor has reached a comprehensive agreement to settle a consolidated shareholder derivative litigation against a number of Lattice's former and current executive officers and directors.
Mapping custom instructions for the Toshiba media embedded processor (MeP)
Design How-To  
12/21/2005   Post a comment
How to map custom instructions for Toshiba's Media Embedded Processor (MeP) – a programmable platform for creating digital media SoCs – using Celoxica's MeP Developer's Kit.
I'm in Nixi Tube Heaven!
Programmable Logic DesignLine Blog  
12/16/2005   Post a comment
I've just been introduced to the "Mike's Electric Stuff" website, which provides a goldmine of information on early display technologies and other "stuff".
Rounding algorithms we know and love
Programmable Logic DesignLine Blog  
12/16/2005   Post a comment
The mind boggles at the variety and intricacies of the rounding algorithms used for different applications.
Lattice narrows 4Q revenue forecast downward
News & Analysis  
12/15/2005   Post a comment
Lattice Semiconductor narrowed its fourth quarter revenue guidance. The company now expects fourth quarter revenue to be up 1 to 2 percent from third quarter revenue, down slightly from the company's earlier growth forecast of 1 to 3 percent.
How to use register retiming to optimize your FPGA designs
Design How-To  
12/14/2005   Post a comment
This article outlines recommended practices that show you how to qualify an FPGA-based design as a good candidate for register retiming, along with specific examples for optimal performance results.
Mixed-signal FPGA is here to stay!
Programmable Logic DesignLine Blog  
12/13/2005   Post a comment
I've seen a number of devices that might be classed as "field-programmable analog arrays (FPAAs)" appear and disappear, but I think this one is here to stay...
Xilinx ISE 8.1i boosts FPGA performance
Product News  
12/12/2005   2 comments
Xilinx ISE 8.1i with Fmax technology provides enhanced physical synthesis capabilities for Virtex-4 and Spartan-3 FPGA architectures and boosts performance up to 70% over competing solutions.
Xilinx FPGA suite release promises performance improvement
News & Analysis  
12/12/2005   Post a comment
Programmable logic supplier Xilinx released version 8.1i of its Integrated Software Environment FPGA design tool suite.
Libero design environment supports Actel's mixed-signal FPGA
Product News  
12/12/2005   Post a comment
Libero IDE 7.0 and starter kit allow designers to fully exploit the capabilities of Actel's mixed-signal FPGA, the Fusion programmable system chip (PSC).
Mixed-signal FPGA from Actel unlocks new design possibilities
Product News  
12/12/2005   1 comment
Actel's mixed-signal Fusion FPGA features highly integrated analog peripherals, Flash memory, and FPGA fabric with soft ARM and 8051 MCU cores in a single programmable system chip (PSC).
Actel lowers 4Q revenue forecast
News & Analysis  
12/9/2005   Post a comment
Shares of Actel declined in after-hours trading after the programmable logic maker lowered its fourth quarter revenue forecast.
QuickLogic starts shipping low-power PolarPro FPGAs
Product News  
12/7/2005   Post a comment
Drawing less than 10 micro-amps of standby current, QuickLogic say that PolarPro devices exhibit ASIC-like power consumption while providing the flexibility of field programmable logic.
OCP is the one for me!
Programmable Logic DesignLine Blog  
12/7/2005   Post a comment
Connecting IP cores together sounds easy if you say it quickly and wave your arms around a lot, but connecting these little scamps together is a non-trivial task.
OCP-based memory access arbitration for a digital sampling oscilloscope
Design How-To  
12/7/2005   Post a comment
Using the open core protocol to implement a multi-port access memory with a single port SRAM for use in a digital sampling oscilloscope.
Toshiba and Xilinx to develop 65nm FPGAs
News & Analysis  
12/6/2005   Post a comment
Companies to build on Toshiba's production of high-performance 65nm FPGA prototype wafers in preparation for next-generation Xilinx product.
UMC and Xilinx to develop 65nm FPGAs
News & Analysis  
12/6/2005   Post a comment
Xilinx and UMC extend long-term manufacturing relationship to 65nm and below; 65nm prototype wafers currently being produced at UMC's 300mm fab.
Actel claims first 'fully qualified' military-standard 883B FPGAs
News & Analysis  
12/6/2005   Post a comment
Programmable logic supplier Actel announced the availability of what the company called the industry's first fully qualified military-standard 883B flash-based field-programmable gate arrays.
First MIL-STD-883B qualified FLASH-based FPGAs ship
Product News  
12/6/2005   Post a comment
Actel strengthens military offering with fully-qualified flexible and reprogrammable platform.
Flash-based FPGAs comply with MIL-STD 883 Class B spec
Product News  
12/6/2005   Post a comment
Actel Corp.'s ProASIC Plus FPGAs have passed extensive testing at extreme conditions to achieve compliance with MIL-STD 883 Class B and qualify for use in high-reliability defense applications, such as military avionics and weapons systems.
Zero-delay programmable clock generators
Product News  
12/6/2005   Post a comment
New clock generators, which support DDR II, QDR II and many telecom clocking applications, are ideal for clock generation and distribution in backplane line cards.
Xilinx plans independent R&D center in India
News & Analysis  
12/6/2005   Post a comment
Xilinx Inc., which has an engineering team at CMC Ltd. at Hyderabad, India, plans to shift the staff to an independent Indian R&D subsidiary in 2006.
Xilinx inks 65-nm foundry agreements with UMC, Toshiba
News & Analysis  
12/6/2005   Post a comment
Xilinx announced the extension of foundry relationships with Toshiba and UMC to include 65-nanometer technology.
Altera affirms fourth quarter guidance
News & Analysis  
12/5/2005   Post a comment
Programmable logic supplier Altera reaffirmed revenue guidance for the fourth quarter, forecasting company revenue would be in the range of $286 million to $297 million.
LSI Logic releases RapidChip SOC prototyping platform
Product News  
12/5/2005   Post a comment
LSI Logic released a RapidChip system-on-a-chip prototyping platform based on the ARM926EJ-S processor.
Pondering a floating-point problem
Programmable Logic DesignLine Blog  
12/5/2005   Post a comment
You don’t realize what you don’t know until you try to explain it to someone else!
Lattice offering zero-delay clock generator devices
News & Analysis  
12/5/2005   Post a comment
Lattice Semiconductor released the ispClock 5600A second generation family of enhanced zero-delay clock generators.


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