Altera claims fastest, largest PLDs with up to 40% speed improvement News & Analysis 2/11/2002 Post a comment SAN JOSE -- Altera Corp. today announced it has developed the industry's fastest and largest programmable logic devices with the launch of a new series, called Stratix, which offers up to 10 megabits of RAM and 114,140 logic elements on a chip. The new series will offer a 40% speed improvement over the company's previous generation of PLDs, said Altera.
21st Century Slide Rules with Logarithmic Arithmetic Design How-To 2/6/2002 Post a comment Using the Logarithmic Number System (LNS) as an alternative to fixed- and floating-point arithmetic reduces multiplication, division, and square root implementation while improving power and area. Mark G. Arnold of the University of Manchester discusses three forms of LNS along with a Verilog implementation of a linear-Lagrange interpolator targeted for an FPGA.
FPGA-Based FIR Filters using Distributed Arithmetic Design How-To 2/4/2002 Post a comment You employ Distributed Arithmetic techniques to save resources in multiply-and-accumulate (MAC) structures implementing DSP functions. M. Martinez-Peiro and fellow authors from the Universidad Politecnica de Valencia, Spain, describe three types of FPGA-based FIR filters they designed using DA methodology, along with a comparison of filter performance.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...