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Content tagged with FPGA/PLD/CPLD
posted in February 2002
Researchers challenge conventional FPGA approaches
News & Analysis  
2/28/2002   Post a comment
Researchers from leading universities and programmable-logic companies gathered at FPGA2002 this week to poke holes in the conventional wisdom that has guided field-programmable gate array design since its inception.
Altera updates guidance on revenue and profit margins
News & Analysis  
2/27/2002   Post a comment
Altera Corp. today said it expects first-quarter revenue to grow between 3% and 5% sequentially, to approximately $170 million, based on sales in January and February and orders for March.
Spin-logic gates point to low-power FPGA
News & Analysis  
2/22/2002   Post a comment
A German research team has developed logic gates based on magnetoresistive elements that could end up providing low-power, dynamically reconfigurable circuits.
Xilinx ups revenue guidance to 10% sequential growth in quarter
News & Analysis  
2/21/2002   Post a comment
SAN JOSE -- Xilinx Inc. today became the latest chip supplier to bump up its revenue estimates for the current fiscal quarter. The company said it now expects a 10% sequential increase in revenues from $228.8 million in the last fiscal quarter, ended Dec. 31.
Altera looks to regain PLD crown with Stratix
News & Analysis  
2/11/2002   Post a comment
Eight months ago, when Altera Corp. pledged to get closer to its top customers, the seeds had already been planted for a development the company now claims will redefine the programmable logic landscape.
Altera claims fastest, largest PLDs with up to 40% speed improvement
News & Analysis  
2/11/2002   Post a comment
SAN JOSE -- Altera Corp. today announced it has developed the industry's fastest and largest programmable logic devices with the launch of a new series, called Stratix, which offers up to 10 megabits of RAM and 114,140 logic elements on a chip. The new series will offer a 40% speed improvement over the company's previous generation of PLDs, said Altera.
21st Century Slide Rules with Logarithmic Arithmetic
Design How-To  
2/6/2002   Post a comment
Using the Logarithmic Number System (LNS) as an alternative to fixed- and floating-point arithmetic reduces multiplication, division, and square root implementation while improving power and area. Mark G. Arnold of the University of Manchester discusses three forms of LNS along with a Verilog implementation of a linear-Lagrange interpolator targeted for an FPGA.
FPGA-Based FIR Filters using Distributed Arithmetic
Design How-To  
2/4/2002   Post a comment
You employ Distributed Arithmetic techniques to save resources in multiply-and-accumulate (MAC) structures implementing DSP functions. M. Martinez-Peiro and fellow authors from the Universidad Politecnica de Valencia, Spain, describe three types of FPGA-based FIR filters they designed using DA methodology, along with a comparison of filter performance.


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