NXP delivers ULPI Hi-Speed USB transceivers for mobile phones Product News 2/26/2007 Post a comment NXP Semiconductors announced the availability of its UTMI+ Low-Pin Interface (ULPI) Hi-Speed USB transceivers, developed for mobile phone designs. The family contains four membersISP1504x1, ISP1508, ISP1702 and ISP1703all of which are compliant with industry specifications, including ULPI Rev. 1.1, USB On-the-Go (OTG) Rev. 1.2 and USB Rev. 2.0.
System simulation speeds application development Design How-To 2/26/2007 Post a comment Developing applications for a wide range of mobile terminals can be a major headache for software engineers. System simulation now provides a way to develop and test software running on a virtual platform long before the hardware is available. Mark Snook explains.
SEC ends Altera stock option probe News & Analysis 2/20/2007 Post a comment Altera Corp. today said the Securities and Exchange Commission has ended its investigation of the company's historical stock option awards without recommending any enforcement action.
Altera posts higher Q4 revenue; expects Q1 dip News & Analysis 2/14/2007 Post a comment Altera posted a net income of $99.9 million for the fourth quarter of 2006, an increase of 14 percent sequentially and 43 percent year-to-year. The company's net revenue for the quarter of $317.4 million was down 7 percent sequentially but up 13 percent year-to-year.
Video color space converter design using mixed-signal via-configurable ASICs Design How-To 2/9/2007 Post a comment Mixed-signal via-configurable ASIC technology gives designers the ability to develop fully integrated mixed-signal ASICs without the lengthy development cycles, high NREs, high risk, and extended fabrication times associated with full-custom mixed-signal IC development. Designing a complete video color space converter becomes easier, for example, with mixed-signal via-configurable ASIC.
Generate FPGA accelerators from C Design How-To 2/8/2007 Post a comment A simple FFT, generated as hardware from C language, illustrates how quickly a software concept can be taken to hardware and how little you need to know about FPGAs to use them for application acceleration.
FPGA transceiver test goes on-chip through Windows Product News 2/7/2007 Post a comment Here's a cool way to test and optimize high-speed serial links implemented in Xilinx RocketIO multi-gigabit transceiver-laden FPGAs. Agilent's E5910A serial link optimizer combines Windows measurement and analysis software with Xilinx intellectual property and the popular JTAG communication infrastructure.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments