Researchers tout foldable, stretchable Si circuits Product News 3/28/2008 1 comment Researchers at the University of Illinois have developed a new form of stretchable silicon integrated circuit that can wrap around complex shapes such as spheres, body parts and aircraft wings, and can operate during stretching, compressing, folding and other types of extreme mechanical deformations, without a reduction in electrical performance.
HD video line buffering in FPGA Design How-To 3/28/2008 Post a comment Complex video processing algorithms -- encoding, motion estimation, and scaling -- implemented using FPGAs need access to various pixel values within a single frame or across multiple frames. The required video line buffers within an FPGA make video applications memory intensive.
Read Arthur C Clarke's geostationary satellite article News & Analysis 3/20/2008 Post a comment Eutelset SA (Paris, France) has paid tribute to science fiction writer Sir Arthur C. Clarke as the "father of the geostationary orbit." In October 1945, long before he broke through as a fiction writer Clarke published an article in the U.K. journal 'Wireless World' that mapped out the potential of the geostationary orbit for satellite communications.
"Dialectize" any webpage Programmable Logic DesignLine Blog 3/19/2008 Post a comment Have you ever wondered what a website like CNN would look like in a redneck dialect (or Jive, Cockney, Sweedish Chef, ...)? Well, now you can see!
Zuverlaessig und schnell: Monos-Flash Design How-To 3/17/2008 Post a comment Embedded Non-Volatile-Memory (NVM) ist eines der wichtigsten Technologieelemente in der Mikrocontrollerwelt, denn die CPU-Kerne sind inzwischen so schnell, dass die Leistung des Systems oft mehr vom Speichersystem abhaengt als vom Kern. Ausserdem ist das NVM-Modul oft im Fokus der Qualitaetsspezialisten, denn es gilt landlaeufig als ein Modul mit Qualitaetsrisiken. Renesas Technologys MONOS Flash sorgt fuer Geschwindigkeit und Zuverlaessigkeit.
DSP system design, part 1: The basic laws Design How-To 3/17/2008 Post a comment Here are ten laws that guide DSP system development. Topics covered include economies of scale and experience effect, DSPs vs. FPGAs, fixed- vs. floating-point, and RTOSs and algorithm libraries.
Actel combines low power and high I/O Product News 3/17/2008 Post a comment In order to address the needs of portable designs in industrial, medical and instrumentation applications, Actel has introduced a new family of low-power FPGAs. Sporting the same low power consumption as the company's established Igloo family, Igloo plus devices are equipped with more I/O lines and a 'Flash Freeze' bus hold option.
Happy Pi day! Programmable Logic DesignLine Blog 3/14/2008 2 comments Yes, it's that time of the year again, March 14 when we celebrate the mathematical constant Pi (after all, where would we be without it?)
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments