Embedded Systems Conference
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Content tagged with FPGA/PLD/CPLD
posted in April 2013
Slideshow: DESIGN West gets virtual Mars rover tour
News & Analysis  
4/23/2013   4 comments
A NASA engineer provided a design review of the guts of the Mars Rover and the systems that safely set it down on the red planet.
Altera announces new Cyclone V SoC development kit
Product News  
4/22/2013   3 comments
Available for ordering now, new kit Includes Altera SoC EDS featuring ARM DS-5 Altera Edition toolkit.
Japanese electronics industry debates future amid turmoil
Blog  
4/22/2013   39 comments
Japanese engineers from competing electronics companies gather in one room to exchange punches, parries, and predictions for Japan's electronics industry.
Xilinx, the Embedded Vision Alliance Summit, and DESIGN West 2013
Product News  
4/18/2013   Post a comment
Presentations and demonstrations highlight combination of SoC silicon, tools, and IP resulting in smarter embedded vision solutions.
Chips vulnerabilities just waiting to be exploited
Blog  
4/16/2013   Post a comment
When hackers got into a mil-grade FPGA, alarm bells went off. The vendor says what they found was a key security feature, but concern remains.
Altera turns to TSMC's embedded flash process
Design How-To  
4/16/2013   Post a comment
FPGA vendor is planning non-volatile programmable devices targeting high-volume applications made using a 55-nm embedded flash manufacturing process.
Altera, AMCC to combine 64-bit processors, FPGAs
Design How-To  
4/15/2013   Post a comment
FPGA and networking chip vendors agree to work together on chips and software for data centers.
HP Moonshot software-defined server captures TI
News & Analysis  
4/8/2013   7 comments
Texas Instruments joined the list of x86 and ARM vendors that eventually will catch a ride in HP's Project Moonshot systems, now shipping with Intel Atom SoCs.
FPGAs supercharge instrument flexibility
Design How-To  
4/1/2013   Post a comment
A growing number of instrument vendors are giving users the ability to customize internal FPGAs, delivering a significant increase in flexibility and speed.


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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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