First wave of IP support washes over FPGA family Product News 5/31/2005 Post a comment Lattice Semiconductor Corp. has released for its recently announced LatticeXP field-programmable gate array (FPGA) family the first set of IP modules that address the needs of the consumer, computing and communications markets.
Employing Emulation to Speed Wireless Products to Market Design How-To 5/13/2005 Post a comment A wireless semiconductor leader extending the functionality of mobile handsets to include a broad range of media applications selected a hardware emulation solution from Emulation and Verification Engineering (EVE) to parallelize its hardware and software development flows. In this feature article, EVE's Lauro Rizzatti explains the emulation solution and how it is implemented.
Stratix II FPGAs yield more logic capacity, whitepaper says Product News 5/12/2005 Post a comment A whitepaper released by Altera Corp. claims that Stratix II field programmable gate arrays give designers more logic capacity than competing devices. The company said that its Stratix II EP2S180 FPGA contains 5% more 4-input look-up-tables ILUT) than Xilinx Inc.'s Virtex-4 XC4VLX200 device. Altera said that its analysis shows that naming conventions don't always depict the density of a given family.
CoSine SoC relieves DSPs Product News 5/10/2005 Post a comment Micro Memory's CoSine performs real-time field programmable gate array (FPGA) processing in a system-on-chip (SoC). It bridges two high-speed interfaces PCI-X or PCI-Express and Serial Rapid I/O through a multi-port DDR controller, enabling access to a user programmable logic (UPL) block without any difficulty.
FFT Core for Adaptive Cruise Control Using FPGAs Design How-To 5/10/2005 Post a comment Adaptive cruise control can increasingly find its way into cars. In large part, this can be made possible using FPGAs and computer-aided design tools. In this feature article, Christober Rayappan summarizes the important aspects and a general design for Adaptive Cruise Control highlighting the Fast Fourier transform (FFT) module, which consumes a significant portion of the chip.
FPGA-to-ASIC conversion service expanded for space applications Product News 5/9/2005 Post a comment Atmel Corp. is expanding its conversion service so that engineers can transform existing space field programmable gate array (FPGA) designs into cost-effective radiation hardened ASICs with shortened lead times. The service is expected to generate cost and power consumption savings of 80% and 70%, respectively, according to the company. It offers a pin-to-pin replacement solution for existing space FPGAs, eliminating expensive board redesign.
Reconfigurable Processors: Changing the Systems Design Paradigm News & Analysis 5/3/2005 Post a comment System designers are always looking for the most efficient methodology to get their products to market. When presented with a new algorithm, they have to juggle a variety of constraints to get that algorithm implemented in silicon. None of the existing solutions have provided all the features that they crave. Dinesh Venkatachalam of Legend Silicon asserts that is changing; a new class of devices called reconfigurable processors seems to finally provide a solution that seems to meet all the requi
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments