Xilinx responds to Altera's FPGA benchmarks
Programmable Logic DesignLine Blog 5/30/2008 2 comments
The folks at Xilinx say that they've re-run the tests with different tool settings and, overall, the Xilinx software solution with Synplify Pro and ISE 10.1 dominates.
ST moves SPEAr SoCs to 65nm
Product News 5/29/2008 Post a comment
By transferring the SPEAr family to 65-nm process technology, ST's SoC can integrate an advanced ARM926EJ-S processor core with two 16k memory caches, running at 333MHz, for data and instructions and up to 300,000 gates (ASIC-equivalent) of embedded configurable logic.
Computer models how nanoparticles harm cells
News & Analysis 5/28/2008 Post a comment
Named for Buckminster Fuller, buckyballs--tiny nanoparticles composed of just 60 carbon atoms (carbon-60)--can enter cells and accumulate to cause damage, according to research scientists at two universities.
Beetle solves photonic-crystal mystery that's bugged researchers
News & Analysis 5/22/2008 Post a comment
Semiconductor makers should take a hint from Mother Nature when pursuing photonic crystals for optical computing, according to University of Utah researchers studying the Brazilian beetle: this bug's eerie iridescence is evidence of its unique photonic lattice structure--called the "champion" architecture in photonic circles.
$200 million for one FPGA?
Programmable Logic DesignLine Blog 5/20/2008 2 comments
Thus far I haven't seen the pricing for Altera's new 40nm Stratix IV FPGAs, but if we were to extrapolate from an analog device I just saw, the result would make your eyes water!
Massively parallel processing arrays (MPPAs) for embedded HD video and imaging (Part 1)
Design How-To 5/16/2008 Post a comment
An MPPA having hundreds of processors can simplify video and imaging software development for embedded applications. Each processor in an MPPA is strictly encapsulated, accessing only its own code and memory. This architecture provides a very different programming model, one where each processor devotes separate channels for each type of input and output data it needs to communicate with other processors, and there are no shared memory bottlenecks.
Making design choices between DSP and FPGA
Design How-To 5/13/2008 Post a comment
System designers face a number of key questions during the architecture phase of their project. Increasingly, one of those questions is whether to use a field-programmable gate array or a digital signal processor.