Gartner bumps up '09 chip sales forecast News & Analysis 5/28/2009 Post a comment Market research firm Gartner issued a revised semiconductor industry revenue forecast that projects 2009 revenue will not fall quite as sharply as the firm predicted in February, thanks to better-than-expected first quarter PC sales.
Startup Netronome rolls new family of programmable network processors Product News 5/28/2009 Post a comment Programmable chip vendor Netronome Systems announced the availability of a family of network processors said to remove the barriers to unified computing architectures by combining high-performance network, content and security processing with general purpose processors, such as Intel's IA, through I/O virtualization.
Shameless plug Programmable Logic DesignLine Blog 5/27/2009 Post a comment This is just a note to encourage anyone who hasn't checked out Max Maxfield's Fundamentals of Mixed-Signal FPGAs course to do so without delay.
10 FREE copies of my Bebop book! News & Analysis 5/26/2009 Post a comment My publisher is offering 10 free copies of the only electronics book where you can simultaneously learn about state machines, musical socks, Reed-Muller logic, and the best time of the day to eat smoked fish!
Assessing FPGA DSP Benchmarks at 40 nm Design How-To 5/21/2009 Post a comment Independent and partisan benchmark results are often difficult to navigate, yet understanding and using reliable device benchmarks for system decisions is essential. While individual benchmark results may be insufficient for making device decisions on a standalone basis, this feature will help designers understand the trends and factors that make up the results of benchmarking studies.
The design debate: Art versus science Programmable Logic DesignLine Blog 5/20/2009 4 comments Ask a chip designer if the work he or she does is an art or a science and you will more than likely hear the former. But Naveed Sherwani, the outspoken president and CEO of fabless ASIC vendor Open-Silicon, takes issue with that.
Did you see that? News & Analysis 5/20/2009 Post a comment Those cheeky chaps in the UK have made a bid to host Super Bowl 2014 in London, England (I kid you not!)
Wafer shipments fell 56% in Q1, says SEMI News & Analysis 5/20/2009 Post a comment Shipments of silicon wafers fell by 56.5 percent to 940 million square inches compared to 2,163 million square inches in the same quarter a year before, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.
Cadence rolls tools to speed design process Product News 5/19/2009 Post a comment At its European user meeting CDNLive, EDA software vendor Cadence Design Systems has introduced two tools aiming at speeding up the design process. The tools attack on two different points: One provides a virtual hardware platform for software/hardware co-development, the other one speeds PCB routing for FPGA solutions.
Programmable clock management increases source synchronous throughput Design How-To 5/13/2009 Post a comment This article examines the features of a dynamically adjustable programmable skew clock chip and proposes a scheme that compensates for various limitations and enables increasing source synchronous communication speed while maintaining reliability. It considers the factors limiting source synchronous communication speed, details a dynamically adjustable skew clock chip architecture, and proposes a source synchronous communication based on it.
What does software firm want with MathStar? Programmable Logic DesignLine Blog 5/13/2009 Post a comment Why is PureChoice Inc., a vendor of building-performance reporting software, trying to buy MathStar for around $9.5 million? And why hasn't the defunct programmable logic vendor's board responded?
Octasic taps Altera exec as CEO News & Analysis 5/12/2009 Post a comment Octasic Inc., a developer of media processing and wireless solutions, announced that Robert Blake has been appointed chief executive.
Blake recently served as vice president of consumer and automotive business at Altera Corp.
Finding new markets through ratification Design How-To 5/12/2009 Post a comment Following the recent introduction of its latest silicon, Xilinx has announced a new version of its design environment, ISE 11.1. Will this prove to be the stimulus FPGA technology needs to penetrate new markets?
Pigeon Point offers starter kits Product News 5/12/2009 Post a comment Pigeon Point Systems, a subsidiary of Actel, introduced a MicroTCA carrier management controller board management reference starter kit based on Actel's Fusion mixed-signal FPGA and a module management controller reference starter kit based on the Renesas H8S/2472 microcontroller.
IP vendor buys LDPC assets News & Analysis 5/11/2009 Post a comment RAD3 Communications, a communications IP vendor, acquired the low-density parity-check code IP assets of Raithlin Semiconductor. Rad3 declined to disclose the financial terms of the deal.
Optimizing Xilinx FPGAs for power Design How-To 5/6/2009 Post a comment This article will describe ways designers can leverage an FPGA's programmability and use related tools to accurately estimate power and then employ optimization techniques to make their FPGA designs and the PCBs that contain them much more power efficient.
Patent strike? Programmable Logic DesignLine Blog 5/6/2009 Post a comment In case you've missed it, there has been a fascinating exchange about the broken U.S. patent system taking place on the pages of EE Times over the past couple weeks.
System ICs to return to growth in Q3, iSuppli says News & Analysis 5/5/2009 Post a comment The market for system ICs--including ASICs, application-specific standard products and programmable logic devices--is poised to return to sequential growth in the third quarter after watching its revenue fall by nearly one third over the past six months, according to market research firm iSuppli.
FPGA startup crunch: SiliconBlue looks to break new ground News & Analysis 5/4/2009 1 comment SiliconBlue Technologies, a four-year old startup backed by $40 million in venture capital funding, is aiming to buck the odds and thrive with low-cost field programmable gate arrays in a product market that has traditionally shunned programmable logic: battery-based handheld consumer products.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments