What am I holding in my hand? Programmable Logic DesignLine Blog 7/22/2008 2 comments Close, but no cigar - it's actually an $84.95 book that provides a hands-on introduction to Verilog synthesis and FPGA prototyping and I'm giving it away...
Team claims advance with paper based transistors News & Analysis 7/22/2008 Post a comment A group of researchers at the Centro de Investigação de Materiais within the New University of Lisbon, Portugal, claim they have made the first Field Effect Transistor with a cellulose fiber based paper "interstrate" layer.
Solve leakage and dynamic power loss Design How-To 7/16/2008 Post a comment Achieving higher performance and integration requires lower process geometries and higher clock frequencies, and aggressive power management techniques. Both leakage and dynamic power loss must be accounted for to successfully design for efficiency. Here are techniques to manage energy at the system level.
Xilinx showcased at 2008 IEEE Nuclear and Space News & Analysis 7/10/2008 Post a comment Xilinx logic solutions enabling space applications will be showcased at the 2008 IEEE Nuclear and Space Radiation Effects Conference (NSREC) at the JW Marriott Starr Pass Resort & Spa in Tucson, Arizona from July 14-18.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments