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Content tagged with FPGA/PLD/CPLD
posted in August 2007
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Using HW emulators to get HW/SW right the first time on the Sun UltraSPARC T1 processor
Design How-To  
8/8/2007   Post a comment
The methodology, tools, and techniques used to address Sun's UltraSPARC T1 system-level verification challenges and deliver a high quality product in a timely manner.
Analysis: Atmel's customizable microcontrollers
Design How-To  
8/8/2007   Post a comment
Atmel's chips claim to beat FPGA/CPU combos on cost, performance, and power. BDTI explains why these claims could be true.
DDR2-400 hardware-verified reference design for Xilinx Spartan-3 FPGAs
Product News  
8/7/2007   Post a comment
Free reference design enables designers to quickly implement 400 Mbps DDR2 SDRAM interfaces with Xilinx Spartan-3 FPGAs.
PCI-SIG compliant development kit for Altera's Arria GX FPGAs
Product News  
8/7/2007   Post a comment
Altera's Arria GX FPGA low-cost development kit is certified PCI-SIG compliant for x1 and x4 PCI Express solutions.
Mega-cool USB-based turntable
Programmable Logic DesignLine Blog  
8/7/2007   Post a comment
Save your old vinyl records - convert them to MP3 or WAV files using this USB-based record deck.
Microchip launches chip Wiki
Programmable Logic DesignLine Blog  
8/6/2007   Post a comment
New site allows engineers, students, and professors to collaborate online and share information on semiconductor products, applications, and best practices.
Historic Phoenix Mars mission flies with Actel RTAX-S FPGAs
News & Analysis  
8/6/2007   Post a comment
Low-power Actel RTAX-S space FPGAs used in battery- and solar-powered mission-essential instruments to acquire and process vital environmental data.
New system management solution starts at $1.20 for embedded applications
Product News  
8/6/2007   Post a comment
Reference design using combination of Actel's mixed-signal Fusion PSC and CoreABC soft micro brings intelligent system and power management to the masses.
Chip makers, researchers dish on hottest chips, interconnects
Product News  
8/6/2007   Post a comment
The Hot Chips and companion Hot Interconnects conferences provide a peek inside the leading multicore processors as well as research into the on- and off-chip networks that those future microprocessors may use.
Designers flow with debug flux
Design How-To  
8/6/2007   Post a comment
Embedded systems designers are facing both gradual and abrupt changes in their debugging tools. On the gradual side, tools are following general design trends and moving toward standardized, open systems. But a left turn may be in the works, as tool developers add wireless connections to embedded debug.
Israeli researchers tout model of time machine
News & Analysis  
8/6/2007   Post a comment
Researchers at the Technion University (Haifa, Israel) claim they have developed a theoretical model of a time machine that, in the distant future, could enable future generations to travel into the past.
The best "computing universe" diagram ever!
Programmable Logic DesignLine Blog  
8/3/2007   Post a comment
I'm the victim of my own success; folks like my "computing universe" diagram and paper so much that they keep on asking me to change them.
If evolution works, why are there so many idiots?
Programmable Logic DesignLine Blog  
8/2/2007   1 comment
As Albert Einstein once said: "Only two things are infinite - the universe and human stupidity, and I'm not so sure about the universe."
FPGA-based hardware acceleration of C/C++ based applications - Part 2
Design How-To  
8/1/2007   Post a comment
Dan Poznanovic from SRC Computers explains how the SRC Carte programming environment allows application programmers to write and port applications to a reconfigurable platform.
When FPGA I/O design becomes a necessity
Programmable Logic DesignLine Blog  
8/1/2007   Post a comment
How to overcome the challenges of rising device complexities and higher costs when integrating programmable logic devices on the PCB.
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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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