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Content tagged with FPGA/PLD/CPLD
posted in September 2006
Xilinx extends ISE 8.2i to include support for largest 65-nm FPGA
Product News  
9/29/2006   Post a comment
Xilinx has made available a downloadable extension to the 8.2i Integrated Software Environment (ISE) Foundation tool suite, allowing access to the Virtex-5 LX330, the industry's largest 65-nm FPGA.
Tech Tutorial: Design considerations for 500W Class D automotive subwoofer amplifiers
Design How-To  
9/28/2006   1 comment
Class D designs promise higher output power within a given auto electronics system volume. But converting to a Class D from a Class AB amp is challenging because the modes of operation and circuit protection schemes are significantly different.
Free reference design simplifies integration of 7:1 LVDS interfaces
News & Analysis  
9/27/2006   Post a comment
Pre-engineered I/O components for LatticeECP2 and LatticeECP2M FPGAs simplify implementation and reduce both component count and system cost.
Altera and Northwest Logic deliver 667-Mbps DDR2 SDRAM interface solution
Product News  
9/27/2006   Post a comment
This interface combines Altera's auto-calibration DDR2 PHY and Northwest Logic's full-featured DDR2 SDRAM Controller Core.
Free reference design integrates display interface in Lattice FPGAs
Product News  
9/27/2006   Post a comment
Check out this free reference design from Lattice Semiconductor. The reference design illustrates how to use the pre-engineered I/O components within its low cost LatticeECP2 and new LatticeECP2M FPGA families to implement the 7:1 source synchronous LVDS interfaces commonly found in display applications.
Building SCA-compliant software-defined radios
Design How-To  
9/27/2006   Post a comment
This article explains the basics of the Software Communications Architecture (SCA) standards for software-defined radio (SDR). It also explains how to choose between custom and off-the-shelf hardware, as well as the role of FGPAs in an SCA-compliant SDR system.
How to use CPLDs to manage average power consumption in portable applications
Design How-To  
9/27/2006   Post a comment
This article focuses on using low power CPLDs to manage average power consumption for FPGAs and other devices in portable products.
Ultra-low-cost programmable power management
Product News  
9/26/2006   Post a comment
Lattice has launched an ultra-low-cost programmable power management solution that is ideally suited for handheld systems requiring very low standby power.
QuickLogic launches programmable CE-ATA solution
Product News  
9/26/2006   Post a comment
QuickLogic delivers a programmable CE-ATA storage solution with support for a variety of low power embedded processors.
QuickLogic adds DVD ROM support to its IDE Companion Device
Product News  
9/26/2006   Post a comment
QuickLogic's programmable IDE Companion Device, provides control and interface functionality for mass storage adoption in portable electronics, now supports DVD ROM.
MathStar rolls new family of FPOAs
Product News  
9/25/2006   Post a comment
Fabless programmable logic supplier MathStar introduced its second generation of field programmable object arrays, claiming operational speeds of up to 1-gigahertz. The company claims that this speed is up to four times faster than today's top FPGA architectures, depending on the application.
Pentek's digital receiver board boasts factory-installed DDC
Product News  
9/22/2006   Post a comment
Applications include wideband recording and systems, real-time DSP and software radio systems, and data-acquisition applications for wideband communication.
Designing multi-antenna signal processing for mobile WiMAX
Design How-To  
9/21/2006   Post a comment
This article explains the basics of techniques such as MIMO and adaptive antenna systems, and how to design multi-antenna signal processing hardware. It includes an extensive checklist to use when selecting a DSP.
90-nm FPGAs embed SerDes, physical coding sublayer block
Product News  
9/21/2006   Post a comment
Lattice's latest FPGA family, the ECP2M, consists of low-cost devices that embed high-speed SerDes I/O plus a a pre-engineered Physical Coding Sublayer (PCS) block. At less than $22.95 in 100,000 unit quantities, the ECP2 FPGAs bridge the price/performance gap between low-cost and high-end FPGAs.
How to reduce power using I/O gating (CPLDs) versus sleep modes (FPGAs)
Design How-To  
9/20/2006   Post a comment
Understanding the differences between low power CPLDs (that use built-in I/O gating features to save power) and non-volatile FPGAs (that employ "Sleep Modes").
Serdes available in low-cost, high-volume 90 nm LatticeECP2M FPGAs
Product News  
9/19/2006   Post a comment
Lattice says its new LatticeECP2M 90 nm FPGAs are the first low-cost, high-volume FPGAs to offer embedded serdes.
32-bit embedded processor offered through open source license
Product News  
9/18/2006   Post a comment
Programmable logic supplier Lattice Semiconductor introduced a 32-bit soft microprocessor optimized for Lattice FPGAs. Lattice claims that the LatticeMico32 is unique among the microprocessors offered by FPGA vendors in that the generated microprocessor and selected peripheral HDL code are licensed under Lattice's open source license agreement.
Lattice rolls low-cost FPGAs with embedded serdes
Product News  
9/18/2006   Post a comment
Claiming an industry first, programmable logic supplier Lattice Semiconductor announced a family of low-cost FPGAs offering high-speed embedded serdes I/O plus a pre-engineered physical coding sublayer (PCS) block.
Analyze DSP designs in FPGAs with the z-transform
Design How-To  
9/18/2006   Post a comment
Crafting high-performance DSP algorithm in an FPGA often requires sophisticated design techniques, such as pipelining and overclocking. However, it is difficult to synchronize overclocked pipelines using traditional time-domain analysis. This article presents an alternative method based on the z-transform that lets you analyze DSP algorithms quickly and easily.
Startup defines next-generation FPGA
Product News  
9/18/2006   Post a comment
Startup Velogix Inc. is developing a high-performance programmable-logic platform to run the billions of operations each second.
Fault-robust microcontrollers allow automotive technology convergence: Part 2, fault detection and supervision
Design How-To  
9/14/2006   Post a comment
In automotive, semiconductor technologies and electronic systems are converging into a "car-on-a-chip." However, this convergence results in a new population of faults and failure modes, so how to make such systems more robust?
Lattice narrows guidance
News & Analysis  
9/13/2006   Post a comment
Programmable logic supplier Lattice Semiconductor narrowed its guidance for the current quarter, saying it expects revenue to be up 1 to 3 percent sequentially from second quarter revenue of $62.7 million.
Xilinx lowers sales guidance
News & Analysis  
9/13/2006   Post a comment
Programmable logic supplier Xilinx lowered its quarterly sales forecast for the current quarter, saying it now expects sales to be down 4 to 7 percent sequentially.
Xilinx demos video-over-IP, HD-SDI, H.264 at IBC
Product News  
9/11/2006   Post a comment
Xilinx will be demonstrating multiple FPGA-based solutions for the broadcast industry at the International Broadcasting Conference (IBC) in Amsterdam September 8-12, 2006.
Lattice to debut new 90nm FPGA at the ESC in Boston
News & Analysis  
9/11/2006   Post a comment
Lattice semiconductor will showcase embedded design solutions and debut a new 90nm FPGA at the Embedded Systems Conference (ESC) in Boston.
Altera to feature high-performance solutions at MemCon 2006
News & Analysis  
9/11/2006   Post a comment
Altera will showcase its high-performance memory interface and PCI Express solutions at Denali MemCon 2006 in San Jose CA.
Actel to demonstrate strength of high-reliability FPGAs at MAPLD 2006
News & Analysis  
9/11/2006   Post a comment
Actel Corporation will showcase its nonvolatile FPGAs at the 9th annual Military and Aerospace Programmable Logic Device (MAPLD) International Conference.
Fault-robust microcontrollers allow automotive technology convergence: Part 1, the nature of faults
Design How-To  
9/11/2006   Post a comment
In automotive, semiconductor technologies and electronic systems are converging into a "car-on-a-chip." However, this convergence results in a new population of faults and failure modes, so how to make such systems more robust?
FPGA Architectures from 'A' to 'Z' : Part 2
Design How-To  
9/8/2006   Post a comment
If you are new to FPGAs, there are a bewildering number of different architectures and related concepts; but fear not, because this tutorial explains all.
Hot products: Single-chip cellphone, USB flash drive
Product News  
9/8/2006   Post a comment
The hottest products posted this week at eeProductCenter include a miniaturized AC/DC switching power supply that delivers 1 watt in standby mode, a new USB flash drive line, a single-chip cell phone device that promises double talk time and a 14-bit, 150-MSPS analog-to-digital converter that consumes only 430 mW.
How to get the best cost savings when implementing an FPGA-to-ASIC conversion
Design How-To  
9/6/2006   Post a comment
Planning an FPGA-to-ASIC conversion requires that the ASIC vendor is involved as early as possible in order to achieve the best cost savings.
Xilinx demonstrates Video-over-IP, HD-SDI, and H.264 solutions at IBC 2006
Product News  
9/6/2006   Post a comment
Xilinx is demonstrating its programmable broadcast solutions at IBC 2006, 8-12 September 2006, at the RAI Convention Center, Amsterdam, Netherlands.
Xilinx expands partnership agreement with Nu Horizons
News & Analysis  
9/5/2006   Post a comment
The partnership agreement is expanded to the United Kingdom and Ireland following the recent acquisition of DT Electronics by Nu Horizons.
FPGA maker launches lowest-power device for portable apps
Product News  
9/5/2006   Post a comment
Here's news of Actel's IGLOO FPGAs, which are designed specifically to address the power-sensitive needs of portable applications. IGLOO devices can achieve static power as low as 5-µW and dynamic power consumption up to 60% lower than low-power competitors.


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Rishabh N. Mahajani, High School Senior and Future Engineer

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Rishabh N. Mahajani, High School Senior and Future Engineer
1 Comment
A future engineer shares his impressions of a recent tour of top schools and offers advice on making the most of the time-honored tradition of the college road trip.

Max Maxfield

Juggling a Cornucopia of Projects
Max Maxfield
7 comments
I feel like I'm juggling a lot of hobby projects at the moment. The problem is that I can't juggle. Actually, that's not strictly true -- I can juggle ten fine china dinner plates, but ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
37 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Karen Field

July Cartoon Caption Contest: Let's Talk Some Trash
Karen Field
129 comments
Steve Jobs allegedly got his start by dumpster diving with the Computer Club at Homestead High in the early 1970s.

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