Free reference design integrates display interface in Lattice FPGAs Product News 9/27/2006 Post a comment Check out this free reference design from Lattice Semiconductor. The reference design illustrates how to use the pre-engineered I/O components within its low cost LatticeECP2 and new LatticeECP2M FPGA families to implement the 7:1 source synchronous LVDS interfaces commonly found in display applications.
Building SCA-compliant software-defined radios Design How-To 9/27/2006 Post a comment This article explains the basics of the Software Communications Architecture (SCA) standards for software-defined radio (SDR). It also explains how to choose between custom and off-the-shelf hardware, as well as the role of FGPAs in an SCA-compliant SDR system.
MathStar rolls new family of FPOAs Product News 9/25/2006 Post a comment Fabless programmable logic supplier MathStar introduced its second generation of field programmable object arrays, claiming operational speeds of up to 1-gigahertz. The company claims that this speed is up to four times faster than today's top FPGA architectures, depending on the application.
90-nm FPGAs embed SerDes, physical coding sublayer block Product News 9/21/2006 Post a comment Lattice's latest FPGA family, the ECP2M, consists of low-cost devices that embed high-speed SerDes I/O plus a a pre-engineered Physical Coding Sublayer (PCS) block. At less than $22.95 in 100,000 unit quantities, the ECP2 FPGAs bridge the price/performance gap between low-cost and high-end FPGAs.
32-bit embedded processor offered through open source license Product News 9/18/2006 Post a comment Programmable logic supplier Lattice Semiconductor introduced a 32-bit soft microprocessor optimized for Lattice FPGAs. Lattice claims that the LatticeMico32 is unique among the microprocessors offered by FPGA vendors in that the generated microprocessor and selected peripheral HDL code are licensed under Lattice's open source license agreement.
Analyze DSP designs in FPGAs with the z-transform Design How-To 9/18/2006 Post a comment Crafting high-performance DSP algorithm in an FPGA often requires sophisticated design techniques, such as pipelining and overclocking. However, it is difficult to synchronize overclocked pipelines using traditional time-domain analysis. This article presents an alternative method based on the z-transform that lets you analyze DSP algorithms quickly and easily.
Lattice narrows guidance News & Analysis 9/13/2006 Post a comment Programmable logic supplier Lattice Semiconductor narrowed its guidance for the current quarter, saying it expects revenue to be up 1 to 3 percent sequentially from second quarter revenue of $62.7 million.
Xilinx lowers sales guidance News & Analysis 9/13/2006 Post a comment Programmable logic supplier Xilinx lowered its quarterly sales forecast for the current quarter, saying it now expects sales to be down 4 to 7 percent sequentially.
Hot products: Single-chip cellphone, USB flash drive Product News 9/8/2006 Post a comment The hottest products posted this week at eeProductCenter include a miniaturized AC/DC switching power supply that delivers 1 watt in standby mode, a new USB flash drive line, a single-chip cell phone device that promises double talk time and a 14-bit, 150-MSPS analog-to-digital converter that consumes only 430 mW.
Blog Make a Frequency Plan Tom Burke 17 comments When designing a printed circuit board, you should develop a frequency plan, something that can be easily overlooked. A frequency plan should be one of your first steps ...