Mainstream microprocessors prepare for Level 3 cache News & Analysis 12/15/2000 Post a comment MONTEREY, Calif. Intel Corp. and others are investigating Level 3 cache as a way to juice microprocessor performance. Having exhausted its best X86 design tricks, Intel is looking at ways to boost clock frequency while keeping the number of instructions executed per clock from falling off a cliff. Large Level 3 caches are prime among them.
NEC licenses RISC core from ARM News & Analysis 12/13/2000 Post a comment TOKYO -- Japan's NEC Corp. here today announced that it has become the latest chip maker to license ARM Ltd.'s 32-bit RISC microprocessor core.
Under the terms, NEC has licensed ARM's ARM946E-S family of products. NEC intends to use ARM's RISC core for use in third-generation wireless handsets and other products.
TSMC ships 0.13-micron wafers with new Cyrix MPUs to Via News & Analysis 12/12/2000 Post a comment HSINCHU, Taiwan -- Taiwan Semiconductor Manufacturing Co. here today announced delivery of processed wafers with functioning 0.13-micron microprocessors to foundry customer Via Technologies Inc. According to TSMC, these microprocessor wafers are the foundry industry's first 0.13-micron products to be shipped to a customer.
Lexra takes steps to end MIPS legal battle News & Analysis 12/11/2000 Post a comment MOUNTAIN VEIW, Calif. - MIPS Technologies Inc.'s patent infringement suit against core vendor Lexra Inc. has taken another turn, with Lexra asking a judge to rule in its favor and separately asking the U.S. Patent and Trademark Office to reexamine one of the two MIPS patents Lexra is alleged to violate.
Lexra filed a motion for a summary judgement in the U.S. District Court for the Northern District of California, before U.S. District Judge Saundra Brown Armstrong.
Motorola licenses 32-bit RISC processor line from ARM News & Analysis 12/4/2000 Post a comment AUSTIN, Tex. -- In a move to expand its product portfolio, Motorola Inc. here today became the latest company to license ARM Ltd.'s family of RISC microprocessors for embedded applications.
Under terms of the agreement, Motorola plans to introduce a family of chips based on ARM's 32-bit RISC architecture. These solutions are expect to be introduced over the next 12 months and will include chipsets, software, development tools, and reference platforms.
Transmeta stumbles on Crusoe glitch News & Analysis 12/1/2000 Post a comment SANTA CLARA, Calif. - News of a glitch with its X86-compatible Crusoe processor couldn't have come at a worse time for fledgling startup Transmeta Corp., which is seeking to gain credibility in an Intel-dominated world. Transmeta's stock
tumbled 18% on Wednesday (Nov. 29) and another 10% on Thursday.
The glitch, which forced NEC Corp. to recall a number of notebook computers based on the Crusoe processor, was due to a failure that might occur when a user reinstalls an operating system. NEC str
IP core handles soft errors News & Analysis 12/1/2000 Post a comment Iroc Technologies has developed what it reckons is the first intellectual property (IP) core to handle soft errors caused by alpha radiation.
Drones are, in essence, flying autonomous vehicles. Pros & cons surrounding drones today might well foreshadow the debate over the development of self-driving cars. In the context of a strongly regulated aviation industry, "self-flying" drones pose a fresh challenge. How safe is it to fly drones in different environments? Should drones be required for visual line of sight, as are piloted airplanes? Is the technology advancing faster than we can answer the questions it poses?
Panelists: Chad Sweet, Director of Engineering, Qualcomm; Yannick Levy, VP Corporate Business Development, Parrot; Jim Williams, ex-FAA drone chief; Michael Drobac, Exec. Director, Small UAV Coalition; Moderator: Junko Yoshida, Chief Int'l Correspondent, EE Times