Buffers minimize jitter in clock distribution, differential signal lines News & Analysis 10/30/2002 Post a comment This article - an expanded version of a contribution on High Speed Design which appeared in EE Times' October 7th InFocus Signals section - discusses two different techniques for minimizing jitter: One uses buffering on clock distribution trees; the other uses buffers at each side of a differential signaling line. Cypress engineers explain.
Disciplined Power Management in Backplanes News & Analysis 10/30/2002 Post a comment GTLP-Gunning Transceiver Logic Plus-requires specialized voltage levels, and produces a number of static and dynamic states. It is important to understand how various power supply configurations affect efficiency and parts count. It is possible to adjust the levels of these power supplies, but the designer must recognize the impact on device performance. Fairchild's Eddie Suckow analyzes some of the tradeoff decisions effecting backplane system performance.
Digital multiphase pumps power for CPU cores News & Analysis 10/29/2002 Post a comment While processor core voltages will drop to 1 V and below, current demand will rise, likely topping 150A by 2005, writes these power management engineers. New-generation PC power modules will need to process transients estimated to be 1000 A/ns at the processor, they say. The only way to do this is to stick fingers into the CPU, and anticipate what it needs - a technique they call "digital power." PA offers an early (albeit partial) exposure to what this entails.
Improving DWDM Performance with Optical Signal Processing Design How-To 10/29/2002 Post a comment By combining the capabilities of a digital signal processor (DSP) with a spatial light modulator, designers can build an optical signal processing solution that effectively grooms, filters, adds, drops, and blocks DWDM signals in metro and wide area networking (MAN and WAN) designs.
PROXIM'S Harmony 802.11a WLAN Card: Burning Up The Airwaves Teardown 10/28/2002 Post a comment As standards wars rage on in 802.11 wireless local-area networks, the Proxim Harmony 802.11a card shows the promise of a cost-effective wireless bandwidth adequate for video and data by cranking up wireless data rates to a theoretical 54 Mbits/second and beyond, although actual throughput is lower.
Serial schemes eyed for disk storage Design How-To 10/28/2002 Post a comment The current state of the industry for device-level storage attachment requires system designers to develop multiple solutions for a full range of storage price/performance options.
Robust designs cut vendor hype Design How-To 10/28/2002 Post a comment Over the years, the industry and its customers have been yanked through various vendor-driven interconnect adventures only to be disappointed as reality displaced hype.
Compatibility issue slows PCI Express Design How-To 10/28/2002 Post a comment PCI Express' innovative approach to I/O is fascinating and, when faster versions become available, it may have interesting potential for future applications. However, the current generation of PCI Express doesn't have a strong value proposition.
Advanced switching boosts PCI Express News & Analysis 10/28/2002 Post a comment Data communications and telecommunications systems are converging, placing new requirements on the system building blocks that are at the heart of the communications infrastructure.
On a mission News & Analysis 10/24/2002 Post a comment Twenty years ago, it was an innovation with unrealized potential and a handful of advocates. Today, DSP serves innumerable applications and exerts a gravitational field that has drawn hundreds of silicon IP and software developers into its orbit.
Broadband FH Wireless Radios Solve Last-Mile Gap News & Analysis 10/24/2002 Post a comment Designers developing 2.4 GHz fixed broadband wireless radios must contend with interference from WLANs, microwave ovens, and more. By moving to a FH radio, designers can dodge this interference and provide high-speed Internet links.
Challenges in HyperTransport Verification News & Analysis 10/22/2002 Post a comment As HyperTransport designs proliferate the comm sector, verification will become a bigger issue for equipment and chip designers. Through a solid bus functional model, designers can tackle many of these verification headaches