Breaking News
Internet of Things Designline
posted in November 2002
Page 1 / 3   >   >>
DRAM makers beef up capital budgets
News & Analysis  
11/27/2002   Post a comment
Garbage in / garbage out: Input filters enhance A/D converter measurements
News & Analysis  
11/27/2002   Post a comment
Analog-to-Digital Converters (A/D converters) are capable of quite impressive noise and distortion performance. However, even the best signal generators and synthesizers produce signals that are not spectrally pure enough to evaluate noise and distortion performance of A/D converters. A National apps guy reminds us that even the best test set ups can benefit from an input filter.
Differential Hall-effect sensors aid rotational speed control
News & Analysis  
11/27/2002   Post a comment
The rotational speed of motors with gear teeth can be precisely monitored and controlled with new-generation Hall-effect sensors. BiCMOS technology provides devices with high-sensitivity and speed, and yet small enough to fit inside motor housings or other tight spaces. Allegro's ace applications engineer explains their principles of operation, and provides a guideline for analog signal conditioning.
Making the Switch from ASICs to ASSPs in Ethernet Designs
Design How-To  
11/27/2002   Post a comment
For years, OEM design engineers leaned away from ASSPs in enterprise and provider-edge switch designs. With new silicon arriving and the market becoming more competitive, Ethernet system designers need to rethink their positions on ASSPs.
Diving into the 802.11i Spec: A Tutorial
News & Analysis  
11/26/2002   Post a comment
The 802.11i specification will play a big role in improving the overall security capabilities of current and future WLAN networks. Here's a look at the key technical ingredients of this draft specification.
SST holds fast during industry storms
News & Analysis  
11/25/2002   Post a comment
How Sun reduced cost /supply risk by moving to COT
News & Analysis  
11/25/2002   Post a comment
Last year engineers at Sun Microsystems began a project to source a limited number of ASIC devices through a customer-owned tooling (COT) model.
Designing a high-performance, low-cost switch fabric chip-set using COT
News & Analysis  
11/25/2002   Post a comment
Tau Networks recently announced a T64 switch fabric chipset consisting of two multi-million gate chips.
COT: post design considerations
News & Analysis  
11/25/2002   Post a comment
The proliferation of libraries and intellectual property (IP) in the customer-owned tooling (COT) world has lowered the barrier of entry for those interested in moving to a COT design flow.
COT versus ASIC
News & Analysis  
11/25/2002   Post a comment
COT or ASIC? No brainer for big, fast router market
News & Analysis  
11/25/2002   Post a comment
The router products market — where the average throughput growth is an incredible 2.2X every 18 months — is moving faster than the formidable Moore's Law.
ASIC to COT: knowing your outsourcing options
News & Analysis  
11/25/2002   Post a comment
The fabless model continues to grow as more companies recognize its benefits. The model includes both the customer-owned tooling (COT) and application- specific IC flows.
SST holds fast during industry storms
News & Analysis  
11/25/2002   Post a comment
TI kicks ASIC program into high gear
News & Analysis  
11/25/2002   Post a comment
Multicast Enables Efficient Streaming of Media over IP
News & Analysis  
11/25/2002   Post a comment
Through IGMP protocol, designers can set up a multicast scheme that will efficiently stream video signals over broadband links and provide new revenue generating services in equipment designs.
TI throws its weight into ASIC battle
News & Analysis  
11/22/2002   Post a comment
Packaging Choices for Wireless IC Designs
Design How-To  
11/22/2002   Post a comment
High-frequency chips pose difficult problems for designers looking for cost-effective, non-performance-limiting packages for these chips. Agilent's Chris Mueth discusses the different types of packages that are available, the required characteristics of these packages, and the need to integrate package and chip analysis into a common design flow.
Proper Serdes Selection Solves Serial Backplane Design Woes
News & Analysis  
11/21/2002   Post a comment
As backplanes move into the 6.25-Gbit/s range and beyond, reflections, crosstalk, ISI, and noise become bigger issues for designers. Choosing the right serdes can help combat these problems.
Streamlining the SoC Design Flow
Design How-To  
11/20/2002   Post a comment
New process technologies are fueling ever-shrinking chips of rapidly increasing density and complexity. At the same time, SoC times-to-market are also shrinking. Mentor Graphics' Claudia Relyea describes the challenges facing SoC design teams along with some ideas for streamlining the chip-design flow.
Virtual Concatenation: Knowing the Details Part 2
Design How-To  
11/19/2002   Post a comment
LCAS has become a vital element in the adoption of virtual concatenation in metro and access designs. In this part, we'll take deep look at the benefits and challenges of implementing LCAS.
Xilinx drives Spartan-IIE to high end
News & Analysis  
11/18/2002   Post a comment
AMD delays 90nm processing in Dresden
News & Analysis  
11/18/2002   Post a comment
Xilinx drives Spartan-IIE to high end
News & Analysis  
11/18/2002   Post a comment
UML graphics bridge diverse systems
Design How-To  
11/18/2002   Post a comment
The Unified Modeling Language (UML) is the standard graphical language for specifying the analysis and design of object-oriented software.
UML evolves total system perspective
Design How-To  
11/18/2002   Post a comment
Since its emergence in the mid-1990s as a modeling methodology to allow developers to define, specify and analyze software architectures, the Universal Modeling Language has changed dramatically.
Risks of modeling language design can be managed
Design How-To  
11/18/2002   Post a comment
Despite all the benefits that model based software engineering technology can bring there are many risks as well: How well will your culture adapt to the new approach?
Model approach eclipses code writing
Design How-To  
11/18/2002   Post a comment
Model-based development that puts more emphasis on the design and refinement of a design model, as opposed to software code, is gaining support among software developers.
Forging a real-time spec for models
Design How-To  
11/18/2002   Post a comment
Much has already been written on the topic of applying the Unified Modeling Language to real-time problems, and whether and how UML needs to be extended for this purpose.
Extreme programming ensures robust software systems
Design How-To  
11/18/2002   Post a comment
For the last five years, a software development methodology called Extreme Programming (XP) has been receiving more attention. It is either admired or condemned from a multitude of sources.
Code generation speeds debug cycle
Design How-To  
11/18/2002   Post a comment
The use of executable code generated from a Unified Modeling Language (UML) design model enables early design verification and serves as an effective technology to shorten development time and reduce project risk for embedded systems.
A method for making UML directly executable
News & Analysis  
11/18/2002   Post a comment
In the 1960's we learned how to compile assembly language into machine language.
DDR prices moderate as production output ramps up
News & Analysis  
11/15/2002   Post a comment
A five-month surge in DDR SDRAM prices appears to be leveling off, as chip manufacturers begin to increase their output of the higher-speed memory devices.
Page 1 / 3   >   >>


EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Dr. Duino Diagnostic Shield Deduces Dilemmas in Arduino Shield Stacks
Max Maxfield
1 Comment
As you are probably aware, I'm spending a lot of my free time creating Arduino-based projects, such as my Inamorata Prognostication Engine, my BADASS Display, and my Vetinari Clock.

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)