Garbage in / garbage out: Input filters enhance A/D converter measurements News & Analysis 11/27/2002 Post a comment Analog-to-Digital Converters (A/D converters) are capable of quite impressive noise and distortion performance. However, even the best signal generators and synthesizers produce signals that are not spectrally pure enough to evaluate noise and distortion performance of A/D converters. A National apps guy reminds us that even the best test set ups can benefit from an input filter.
Differential Hall-effect sensors aid rotational speed control News & Analysis 11/27/2002 Post a comment The rotational speed of motors with gear teeth can be precisely monitored and controlled with new-generation Hall-effect sensors. BiCMOS technology provides devices with high-sensitivity and speed, and yet small enough to fit inside motor housings or other tight spaces. Allegro's ace applications engineer explains their principles of operation, and provides a guideline for analog signal conditioning.
Diving into the 802.11i Spec: A Tutorial News & Analysis 11/26/2002 Post a comment The 802.11i specification will play a big role in improving the overall security capabilities of current and future WLAN networks. Here's a look at the key technical ingredients of this draft specification.
COT: post design considerations News & Analysis 11/25/2002 Post a comment The proliferation of libraries and intellectual property (IP) in the customer-owned tooling (COT) world has lowered the barrier of entry for those interested in moving to a COT design flow.
Packaging Choices for Wireless IC Designs Design How-To 11/22/2002 Post a comment High-frequency chips pose difficult problems for designers looking for cost-effective, non-performance-limiting packages for these chips. Agilent's Chris Mueth discusses the different types of packages that are available, the required characteristics of these packages, and the need to integrate package and chip analysis into a common design flow.
Streamlining the SoC Design Flow Design How-To 11/20/2002 Post a comment New process technologies are fueling ever-shrinking chips of rapidly increasing density and complexity. At the same time, SoC times-to-market are also shrinking. Mentor Graphics' Claudia Relyea describes the challenges facing SoC design teams along with some ideas for streamlining the chip-design flow.
UML evolves total system perspective Design How-To 11/18/2002 Post a comment Since its emergence in the mid-1990s as a modeling methodology to allow developers to define, specify and analyze software architectures, the Universal Modeling Language has changed dramatically.
Forging a real-time spec for models Design How-To 11/18/2002 Post a comment Much has already been written on the topic of applying the Unified Modeling Language to real-time problems, and whether and how UML needs to be extended for this purpose.
Code generation speeds debug cycle Design How-To 11/18/2002 Post a comment The use of executable code generated from a Unified Modeling Language (UML) design model enables early design verification and serves as an effective technology to shorten development time and reduce project risk for embedded systems.