Microchip, Chang headline 2009 ACE Award winners News & Analysis 3/31/2009 Post a comment Microcontroller and analog chip vendor Microchip Technology was presented the award for "Company of the Year," one of 11 winners of the 2009 EE Times ACE Awards. Morris Chang, founding chairman of TSMC, was honored with a "Lifetime Achievement Award."
STMicro Mobile App Voltage-Agnostic MEMS-Based Motion Sensor Product News 3/31/2009 Post a comment STMicroelectronics MEMS sensors with a 3-axis accelerometer with absolute analog output for data-integrity protection in hard-disk drives, vibration monitoring and compensation, remote control, as well as motion user interfaces in mobile and gaming devices or portable media players.
FSI cuts jobs, posts loss News & Analysis 3/31/2009 Post a comment Amid the downturn and ongoing losses, fab tool maker FSI International Inc. plans to take several cost-cutting measures, including layoffs.
Altera CEO got $4.1 million in 2008 Programmable Logic DesignLine Blog 3/31/2009 Post a comment The Associated Press reported that Altera CEO John Daane pulled down a compensation package worth $4.1 million last year, an increase of 25 percent over 2007.
The Tao of DSP Signal Processing DesignLine Blog 3/31/2009 1 comment DSP and martial arts have a lot in common. It doesn't matter what tool, hardware or environment you use, having a vision and an understanding of the underlying mechanics needed to get you there is all that matters.
Simplifying BLDC commutation and feedback system Design How-To 3/31/2009 Post a comment In a Brushless DC (BLDC) motor system, an electronic mechanism
is required to commutate the system. Unlike a Brush DC motor system,
the permanent magnet is located at the Rotor and the windings are
located at the Stator. As a result of this setup arrangement, the
windings are required to energize in sequence, to enable smooth
commutation. For the electronic system to determine which windings to
energize, Hall sensor feedback is used to get the current location of
the windings with respect to the
Video: Cisco shows server at Xeon launch News & Analysis 3/31/2009 Post a comment Big data centers are preparing for a shift to 10 Gbit/s Ethernet and some are interested in GPU processing once standards emerge, said a panel of data center managers who are testing Intel's just announced Xeon 5500 processors.
PCI Express on FPGA: A comprehensive guide to available solutions Design How-To 3/30/2009 Post a comment Many end-applications today use an FPGA-based design as an inherent component of their solution. They often require PCI Express as an indispensible feature, to provide a standardized interface with other components in the system. This paper presents an evaluation of the most common methods used for implementing PCI Express in FPGAs.
Albany NanoTech Complex expanded News & Analysis 3/30/2009 Post a comment A $150 million expansion at the College of Nanoscale Science and Engineering's Albany NanoTech Complex will create $1 billion in new investments and 600 high-tech jobs by 2013, according to a statement released by New York Assembly Speaker Sheldon Silver.
Guest blog: Mike Santarini News & Analysis 3/30/2009 3 comments Mike Santarini, a former editor at EE Times and EDN (now publisher of Xilinx user magazine Xcell Journal) makes his first guest blog entry for Programmable Logic DesignLine, warning EDA vendors to get serious about the FPGA business.
Ever hear of CQC? Power DesignLine Blog 3/30/2009 Post a comment Bernard Murphy, Chief Technology Officer of Atrenta Inc., wants to make chip designers aware of continuous quality control.
Intel rolls 45-nm server CPUs News & Analysis 3/30/2009 Post a comment Intel Corp. formally rolls out server versions of its 45-nm Nehalem processors, the Xeon 5500 chips that integrate memory controllers and a high-speed interconnect, taking a page from archrival Advanced Micro Devices which pioneered the approach in x86 chips.
ASICs decline, FPGAs ready to step in Blog 3/30/2009 Post a comment According to market research firm Gartner Inc. FPGAs now have a 30-to-one edge in displacing ASICs in design starts. The firm predicts the trend in 2009 will be exacerbated by the global financial crisis.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments