Shared-Memory Fabrics Meet 10-Gbit Backplane Demands Design How-To 4/23/2003 Post a comment Questions are arising in the sector about a crossbar fabric's ability to provide the scalability and cost required in today's high-seed networking equipment designs. With that in mind, designers should consider making the shift to shared-memory fabric architectures.
ZIF Makes Dual-Band WLAN Radios Practical Design How-To 4/22/2003 Post a comment Supporting 802.11a, b, and g operation in a superhet radio architecture is not a practical solution for today's WLAN radio designers. To reduce component counts, engineers should consider a ZIF approach. Here's why.
DSP Design Services: Finding the Right Development Partner Design How-To 4/22/2003 Post a comment Outsourcing is now common practice in the technology industry. This is in line with the modern business practice of maintaining the core business internally, and outsourcing non-core activities. Outsourcing of DSP projects contain some particular challenges that may not be present for ASICs, PCBs, FPGA, and software development. Shane Tonissen, Calyptech's CTO, identifies the major challenges associated with DSP outsourcing, and provides guidance as to how the right outsource partner can overcom
It's a Switcher - Part 4 News & Analysis 4/21/2003 Post a comment In part 3 of this four-part series, Sanjaya Maniktala examined Buck ICs, the "Type 2s" in his topology. Here, he turns to the sensing schemes that are critical to load regulation. Whether we're looking at negative-to-positive or negative-to-negative transitions, current sensing and better output regulation can be implemented by using an op-amp like an LM324. This final article installment examines where the amplifier can be inserted in the flyback chain.
Analog controller balances power, precision and cost in handhelds News & Analysis 4/21/2003 Post a comment Wearing pulse monitors and other instruments to the health club? Our fascination with gadgets extends from airports and convention centers to the most intimate of settings. These devices have much in common: A CPU and sensor interface that's accurate, cheap, and runs from a coin cell. A Texas Instruments' authority gives details using a glucose meter example.
Power struggle News & Analysis 4/21/2003 Post a comment Look inside any portable or wired system these days and the density of the design is immediately impressive. What is not as readily apparent are the power management issues designers must grapple with as they tie together a growing number of subsystems, all running at different operating voltages.
Design for verification methodology allows silicon success Design How-To 4/18/2003 Post a comment In this detailed whitepaper, Synopsys authors Rindert Schutten and Tom Fitzpatrick set forth a new "design for verification" methodology based on assertions and multi-level interface design. The methodology unites dynamic and formal tools, and leverages verification IP.
Disk drive prices seen headed for further erosion News & Analysis 4/18/2003 Post a comment After a brief respite in the fourth quarter of 2002 and earlier this year, the disk drive market is again facing strong pricing pressures that have forced manufacturers to reinstate sales incentives in an attempt to lure back skittish distributors.
ASIC/ASSP platform speeds development Design How-To 4/18/2003 Post a comment As technology advances, system-on-chip devices tend to absorb and integrate more functionality from surrounding systems. It is rapidly becoming impossible to develop an SoC from scratch: The amount of knowledge and experience required of the design team would make the project unmanageable, prohibitively expensive or would increase the design time so much that the device would be obsolete before its introduction.
Method offers snapshot of SoC operation Design How-To 4/18/2003 Post a comment With an ever-shortening development cycle, and often several generations of products being produced in parallel or in rapid succession, the need for standardized embedded tools and capabilities that enable quick analysis and debug of embedded intellectual property (IP) is a critical factor in keeping system-on-chip verification manageable.
Jitter Impacts on Equalized Link Performance: Part 1 Design How-To 4/17/2003 Post a comment There's no doubt that 5- to 6.25-Gbit/s backplanes will become the de-facto standard in the communication arena. But to get there, designers need to tackle some tough challenges. In Part 1 of this series, we'll examine how time and frequency domain analysis can help.
Duty-cycle is one key to buck converters' output current capability News & Analysis 4/16/2003 Post a comment More thoughts on buck regulators: The most critical factor in DC-DC converter circuits is the load current capability, writes this On Semiconductor apps engineer. Whether you're using an internal or external FET, the sizing of the switch will be a function of its current rating. The overall power supply circuit also depends on the input-output voltage relationship, the inductor value, and switching frequency. Based on one of On's switching regulator circuits, this piece offers advice for picking
It's a Switcher - Part 3 News & Analysis 4/16/2003 Post a comment In part 3 of this four-part series, Sanjaya Maniktala examines Buck ICs, the "Type 2s" in his topology. Here, the Drain/Collector of the FET switch is typically connected to the control sections. Some of the versatility of the LSD cell is lost, he says. But the Type 2 is actually a good choice for positive-to-positive Buck regulators. This article shows how.
As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.
January 2016 Cartoon Caption ContestBob's punishment for missing his deadline was to be tied to his chair tantalizingly close to a disconnected cable, with one hand superglued to his desk and another to his chin, while the pages from his wall calendar were slowly torn away.122 comments