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posted in June 2005
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Datenpfad-Tools schaufeln auf dem Chip Platz frei
News & Analysis  
6/1/2005   Post a comment
Wer beim Chip-Design mit knappen Platzvorgaben kämpfen muss, kann sich jetzt freuen: Das Startup-Unternehmen Arithmatica bringt jetzt seine ersten EDA-Tools auf den Markt, mit denen Entwickler bis zu 40 Prozent Platz im Chip sparen können.
Maxim's new dual linear regulator provides scalable current design
Product News  
6/1/2005   Post a comment
Maxim introduces the MAX8737, a dual, high-power, linear-regulator controller used with external n-channel MOSFETs to generate two independent low-voltage supplies for notebook computers.
AnalogicTech introduces a tri-mode charge pump for high volume cell phone market
Product News  
6/1/2005   Post a comment
Meeting the demanding cost/performance standards of today's mass market consumer cell phones, AnalogicTech has introduced a high efficiency, low noise, constant frequency charge pump for white LED applications.
Meter measures UMTS RF field strength
Product News  
6/1/2005   Post a comment
With increasing public concern over the proliferation of 3G mobile phone towers, this UMTS software upgrade for the Narda SRM-3000 selective radiation meter enables it to measure field strength from individual UMTS cells at a shared antenna site.
Elesta extends switching capacity of safety relay by 50%
Product News  
6/1/2005   Post a comment
The Elesta SGR 282 Z safety relay with 2 forcibly guided change-over contacts according to EN 50205 and has been further improved. Sensitive coils up to 110 V DC with a coil power consumption of approx. 700 mW are now available.
IBM und Chartered setzen auf kompatible 90-nm-Prozesse
News & Analysis  
6/1/2005   Post a comment
Statt Alleingängen setzen IBM und Chartered Semiconductor beim 90-nm-Node auf Teamwork: Beide Chiphersteller wollen künftig eine lückenlose Design-Portabilität für ihre 90-nm-Fabs anbieten.
Smart card groups join forces in Taiwan
News & Analysis  
6/1/2005   Post a comment
The MultiMediaCard Association intends to join forces with a Taiwanese memory card alliance.
Manhattan Routing offers hierarchical timing closure
Product News  
6/1/2005   Post a comment
Manhattan Routing has extended the capability of its Physical Window/Optimization Cockpit timing closure tool to include optimization of hierarchical integrated circuit designs.
From SID, 3D and more
Blog  
6/1/2005   Post a comment
I was pleasantly surprised to see the extent to which small-time, garage-style inventors are still a factor in what is arguably the most cutting-edge aspect of video displays: 3D.
New 3D Displays at SID
Design How-To  
6/1/2005   Post a comment
A number of 3D exhibits were on display at the Society for Information Displays conference in Boston, including some that required no special glasses.
An introduction to semiconductor technologies for power management - Part 1
Design How-To  
6/1/2005   Post a comment
Power management is generally accomplished by a combination of small signal transistors acting as the brain, power transistors acting as solid state switches that control the power flow from the source to the load, and passive components like resistors, capacitors, and inductors, acting as sensing and energy storing elements. Fairchild Semiconductor's director of product planning " and frequent Planet Analog contributor " Reno Rossetti offers this tutorial on the fabrication processes and transi
Wireless transceiver links devices implanted in humans
Product News  
6/1/2005   Post a comment
Zarlink introduces the world's first wireless chip designed specifically for in-body communication systems
Upgraded FPGA design tool boosts logic performance by 15%
Product News  
6/1/2005   Post a comment
The PlanAhead design and analysis tool that supports Virtex-4 platform and Spartan-3 FPGA families has been upgraded with several new features that enable engineers to find and fix problems even earlier in the design process than previous versions. The PlanAhead 7.1 tool's enhancements include metric maps, gate-level floor planning, an intuitive user interface, and improved accuracy of timing analysis.
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