The Give and Take of Designing RISC/DSP Dual-Core SoCs Design How-To 7/31/2002 Post a comment The marriage of DSP and RISC engines on an single chip provides the
muscle you need to handle high-bandwidth video, voice, and data
applications. Jack Shandle discusses some of the issues designers must tackle to successfully implement RISC/DSP dual-core SoCs.
Securing WLAN Links: Part 3 News & Analysis 7/30/2002 Post a comment There's no escaping that WEP is a problem for WLAN designers. In the final part of this series, we'll layout some technology solutions that can help designers enhance security in WLAN systems.
Scaling Optical Modules to 40-Gb Speeds News & Analysis 7/29/2002 Post a comment The call for 4X or 10X speed increases in datacom designs forces optical module manufacturers to evaluate new process technologies, better manage signal integrity, and account for imperfect performance in the existing fiber plant.
Damping of Power-Converter Front-End Averaging Filters Design How-To 7/29/2002 Post a comment The performance of an LC averaging filter at the input stage of an off-line power converter, with and without additional damping, is compared under common transient disturbances. Results suggest that the bulky and costly damping may not be justified for the improvement in performance.
Relaxed rules proposed for early 65-nm processes News & Analysis 7/25/2002 Post a comment Chip designers planning to scale their system-on-chip designs to the 65-nanometer process technology node by the middle of the decade were given fair warning at Semicon West this past week: Steering past delays in lithography, interconnects and other elements crucial to extending Moore's Law will require some tricky navigation.
Rendering hair and fur needs computer graphics muscle News & Analysis 7/24/2002 Post a comment Before they became a checklist item for SoC designs, RAMDACs would convert digital RGB values to a value that lit a CRT phosphor dot - and the rendering engine came up with each RGB value was equivalent to a time-share on a Cray supercomputer. The times have changed, says this computer graphics authority, all the work is done by a single chip - cheap enough to power a kid's gaming machine. Here's how it works. . . using hair and fur as an example.
It's not just 50 ohms: Some termination tips for differential and single-ended amplifiers News & Analysis 7/24/2002 Post a comment Most designers know that it is necessary to terminate a high-speed circuit to avoid reflection. Termination has been applied to digital, communication, RF, and analog circuits for decades. It is easy to place a 50 ohm resistor on an input and think that the job is done. The errors produced by incorrect understanding of termination are subtle and may go unnoticed. The designer may compensate for them by "tweaking" the circuit, when only a little forethought will yield the correct response from th
The Complexities of Designing Compilers for Protocol Stacks News & Analysis 7/24/2002 Post a comment Communication protocols, used to differentiate and to introduce new features into end products, require several attributes, including reusability, portability, and reliability. Novilit's Vladimir Novikov discusses the complex job of designing compilers for communication-protocol stacks.
Securing WLAN Links: Part 2 News & Analysis 7/23/2002 Post a comment The 802.11 specification has some clear authentication discrepancies that create security headaches for WLAN design engineers. In Part 2 of this series, we'll examine the 802.11 authentication mechanisms and the security problems they provide.
Every new design is an ESD test chip Design How-To 7/18/2002 Post a comment The effect of low ESD immunity on a new product introduction can be both obvious and subtle. Manufacturing and test facilities adhere to ANSI standards for ESD protection and handling of chips based on minimum IC ESD immunity requirements.
Test flow speeds up MP3 decoder development to eight weeks Design How-To 7/18/2002 Post a comment In the SoC design and integration methodology of a MPEG1/2 Audio Layer 3 (MP3) decoder chip, a top-down integration flow, combined with a focus on constraint-driven timing analysis, modular simulation and DFT solutions, led to an implementation cycle of only eight weeks.
ADSL2: Taking the Next Step in Broadband Designs Design How-To 7/18/2002 Post a comment The ITU has all but completed the new ADSL2 standards, which delivers improved rate and reach performance, advanced diagnostics capabilities, standby modes, and more to broadband designers. Here's a look at how the spec delivers these capabilities.
Securing Wireless Links: Part 1 Design How-To 7/16/2002 Post a comment Security concerns continue to circle around WLAN systems. In Part 1 of this three-part set, we'll examine the security challenges faced by systems operating over a wireless medium.
Building a base for embedded ROI Design How-To 7/15/2002 Post a comment Participating in the development of standards involves a lot of time, energy and dedication to get the maximum return on investment (ROI). A company needs to be totally dedicated to driving and then using open-architecture standards in its product solutions. To not be totally dedicated would be a great misuse of valuable resources.
In Design Closure, Timing Isn't Everything Design How-To 7/15/2002 Post a comment While timing closure remains a key component of chip design, correct
timing is only one of several design parameters. TechOnLine's Jim
Lipman explains why he thinks EDA tool vendors need to put more effort
into developing high-level tools to help designers meet power and other design specifications.
Real data cuts timing mumbo-jumbo for cascaded PLL designs News & Analysis 7/10/2002 Post a comment PLLs provide the designer with the luxury of re-timing late or early clocks, eliminating the propagation delays that occur when clocks are transported over long distances. But typically there is noise and degradation - jitter - with each PLL in the chain, says this Cypress clocking expert. Here is an excellent example of timing budget measurements that can reduce the impact of noise in your system.
VSIA guidelines assist SoC Signal Integrity News & Analysis 7/9/2002 Post a comment Authors and integrators of intellectual property (IP) are trying to tape out chips without real verification of chip-level signal integrity matters. EDA solutions are complex and inadequate, with capacity-limited extraction tools that run out of steam well before system-on-chip (SoC) design sizes are met.