Breaking News
Internet of Things Designline
posted in July 2002
Page 1 / 2   >   >>
The Give and Take of Designing RISC/DSP Dual-Core SoCs
Design How-To  
7/31/2002   Post a comment
The marriage of DSP and RISC engines on an single chip provides the muscle you need to handle high-bandwidth video, voice, and data applications. Jack Shandle discusses some of the issues designers must tackle to successfully implement RISC/DSP dual-core SoCs.
ICS posts fiscal 4Q gains, but down year-over-year
News & Analysis  
7/30/2002   Post a comment
Integrated Circuit Systems today reported it increased its profits by cutting costs and migrating to higher margin digital consumer products.
Securing WLAN Links: Part 3
News & Analysis  
7/30/2002   Post a comment
There's no escaping that WEP is a problem for WLAN designers. In the final part of this series, we'll layout some technology solutions that can help designers enhance security in WLAN systems.
Infineon joins AMD, UMC in nanometer process effort
News & Analysis  
7/30/2002   Post a comment
Infineon Technologies today joined a codevelopment between chip maker AMD and pure-play foundry UMC for 65nm and 45nm process technology using 300mm wafers.
Scaling Optical Modules to 40-Gb Speeds
News & Analysis  
7/29/2002   Post a comment
The call for 4X or 10X speed increases in datacom designs forces optical module manufacturers to evaluate new process technologies, better manage signal integrity, and account for imperfect performance in the existing fiber plant.
Damping of Power-Converter Front-End Averaging Filters
Design How-To  
7/29/2002   Post a comment
The performance of an LC averaging filter at the input stage of an off-line power converter, with and without additional damping, is compared under common transient disturbances. Results suggest that the bulky and costly damping may not be justified for the improvement in performance.
Relaxed rules proposed for early 65-nm processes
News & Analysis  
7/25/2002   Post a comment
Chip designers planning to scale their system-on-chip designs to the 65-nanometer process technology node by the middle of the decade were given fair warning at Semicon West this past week: Steering past delays in lithography, interconnects and other elements crucial to extending Moore's Law will require some tricky navigation.
Tracking power supply makes split rails from single line
News & Analysis  
7/24/2002   Post a comment
This Maxim circuit generates the bipolar voltages required in many industrial analog applications, as well as contrast-control voltages for an LCD.
Rendering hair and fur needs computer graphics muscle
News & Analysis  
7/24/2002   Post a comment
Before they became a checklist item for SoC designs, RAMDACs would convert digital RGB values to a value that lit a CRT phosphor dot - and the rendering engine came up with each RGB value was equivalent to a time-share on a Cray supercomputer. The times have changed, says this computer graphics authority, all the work is done by a single chip - cheap enough to power a kid's gaming machine. Here's how it works. . . using hair and fur as an example.
Steering Your Way Through Net Processor Architectures
News & Analysis  
7/24/2002   Post a comment
There are a flurry of 10-Gbps network processors on the market today. Here's a guide to steer your way through these architectures, so you can pick the best one for your networking system design.
The Complexities of Designing Compilers for Protocol Stacks
News & Analysis  
7/24/2002   Post a comment
Communication protocols, used to differentiate and to introduce new features into end products, require several attributes, including reusability, portability, and reliability. Novilit's Vladimir Novikov discusses the complex job of designing compilers for communication-protocol stacks.
Securing WLAN Links: Part 2
News & Analysis  
7/23/2002   Post a comment
The 802.11 specification has some clear authentication discrepancies that create security headaches for WLAN design engineers. In Part 2 of this series, we'll examine the 802.11 authentication mechanisms and the security problems they provide.
Testable SoCs
News & Analysis  
7/18/2002   Post a comment
Design for testability: separating the myths from reality
Design How-To  
7/18/2002   Post a comment
The emergence of SoC has been described as a development that will require fundamental changes in the approaches to design-for -testability (DFT).
Every new design is an ESD test chip
Design How-To  
7/18/2002   Post a comment
The effect of low ESD immunity on a new product introduction can be both obvious and subtle. Manufacturing and test facilities adhere to ANSI standards for ESD protection and handling of chips based on minimum IC ESD immunity requirements.
Testing the HyperTransport PHY core
Design How-To  
7/18/2002   Post a comment
Achieving Gigabit data rates is a challenge that can excite the imagination of chip designers.
Test flow speeds up MP3 decoder development to eight weeks
Design How-To  
7/18/2002   Post a comment
In the SoC design and integration methodology of a MPEG1/2 Audio Layer 3 (MP3) decoder chip, a top-down integration flow, combined with a focus on constraint-driven timing analysis, modular simulation and DFT solutions, led to an implementation cycle of only eight weeks.
How systems level considerations impact cost-effective Gigabit Ethernet PHYs
Design How-To  
7/18/2002   Post a comment
The trigger that enabled the transition from Ethernet (10Mb) to Fast Ethernet (100Mb) throughout the data center and eventually to the desktop occurred when IT decision-makers could purchase "10x the performance for 2-3x the price".
SoC testability: Designers confront speed, complexity issues
Design How-To  
7/18/2002   Post a comment
For much of the lifetime of digital IC engineering, testability has been one of those issues that was somebody else's problem.
ADSL2: Taking the Next Step in Broadband Designs
Design How-To  
7/18/2002   Post a comment
The ITU has all but completed the new ADSL2 standards, which delivers improved rate and reach performance, advanced diagnostics capabilities, standby modes, and more to broadband designers. Here's a look at how the spec delivers these capabilities.
Reworking VCXO Architectures for Optical Designs
Design How-To  
7/17/2002   Post a comment
Proposed oscillator architecture delivers -50 dB subharmonic suppression, better than -115 dBc/Hz phase noise spectral density, and better than +/-20-ppm stability, thus improving the performance in Sonet/SDH systems.
Securing Wireless Links: Part 1
Design How-To  
7/16/2002   Post a comment
Security concerns continue to circle around WLAN systems. In Part 1 of this three-part set, we'll examine the security challenges faced by systems operating over a wireless medium.
Lattice to acquire 10Gbits/s serdes developer
News & Analysis  
7/15/2002   Post a comment
Lattice Semiconductor said it will pay $23 million in stock to acquire Cerdelinx Technologies, a developer of OC-192 serdes chips.
Interconnect standards tie embedded networks together
Design How-To  
7/15/2002   Post a comment
For more than a decade, Ethernet has been the computer interconnect of choice. It is used to connect computer servers to client's applications or users.
Distributed switch fabric standards: more performance, choices
Design How-To  
7/15/2002   Post a comment
Mesh topology fabrics are becoming the topology of choice for open architecture systems. A mesh populates point-to-point connections until all nodes have connections to all other nodes.
Next gen ATM designs on existing platforms offer alternative to Ethernet MPLS
Design How-To  
7/15/2002   Post a comment
Now that the initial hype of pure IP-based voice networks has worn off and yielded to the realization of the near term infeasibility of providing carrier-class QoS-based voice services over such networks, attention has returned to ATM.
A look at standard interfaces for carrier-grade applications/platforms
Design How-To  
7/15/2002   Post a comment
In regard to embedded systems for networking and telecom, the term carrier grade availability refers to high probability that a system service, such as a database or telecommunications services gateway, will be operational when required by a client.
Meeting the need for flexible network services
Design How-To  
7/15/2002   Post a comment
Packet processing is nothing new. Both Internet protocol (IP) and asynchronous transfer mode (ATM) routers and switches have been around for some time.
Intelligent platform management interface gives network builders control
News & Analysis  
7/15/2002   Post a comment
Sometimes you have to give up some control to gain control. Sound contradictory? It's really not. For example, initially, CompactPCI systems adhering to the PICMG 2.0 (PCI Industrial Computer Manufacturing Group) standard typically utilized the PCI bus to control and manage card slots.
Next gen networks, open architectures: a "plane" and simple way
Design How-To  
7/15/2002   Post a comment
The infrastructure at the heart of the world's telecommunications networks remained basically unchanged for many years.
Common software architecture to foster NPU ecosystem
Design How-To  
7/15/2002   Post a comment
ASICs are at the heart of today's networks. They provide layer 2 and 3 functionality in everything from fast Ethernet switches in enterprise networks to terabit routers within the network core.
VXS offers switched serial fabric path
News & Analysis  
7/15/2002   Post a comment
Bused embedded compute platforms based on VMEbus and CompactPCI have served the industry well and have built up extensive ecosystems of complementary and competing products.
Optics primed for box-level solutions
News & Analysis  
7/15/2002   Post a comment
Most of today's optical technologies are used to connect network end points outside the box over relatively long distances.
Building a base for embedded ROI
Design How-To  
7/15/2002   Post a comment
Participating in the development of standards involves a lot of time, energy and dedication to get the maximum return on investment (ROI). A company needs to be totally dedicated to driving and then using open-architecture standards in its product solutions. To not be totally dedicated would be a great misuse of valuable resources.
In Design Closure, Timing Isn't Everything
Design How-To  
7/15/2002   Post a comment
While timing closure remains a key component of chip design, correct timing is only one of several design parameters. TechOnLine's Jim Lipman explains why he thinks EDA tool vendors need to put more effort into developing high-level tools to help designers meet power and other design specifications.
Firmware-friendly reset design
News & Analysis  
7/12/2002   Post a comment
Standards Work Focuses on Transparent Operation Over IP
News & Analysis  
7/11/2002   Post a comment
Over the past few years, ITU Study Group 16 has made big strides on the standards front to promote the delivery of multimedia services over IP networks. Here's an update on some of the key developments coming from this organization.
Eye scan saves time with multi-channel signal-integrity measurements
News & Analysis  
7/11/2002   Post a comment
An eye scan mode enhances the functionality of a logic analyzer, making it behave like analog oscilloscope. This capability brings an interesting new design and verification tool to developers of high-speed multiple-bus designs. Aligent's Art Porter shows how.
Real data cuts timing mumbo-jumbo for cascaded PLL designs
News & Analysis  
7/10/2002   Post a comment
PLLs provide the designer with the luxury of re-timing late or early clocks, eliminating the propagation delays that occur when clocks are transported over long distances. But typically there is noise and degradation - jitter - with each PLL in the chain, says this Cypress clocking expert. Here is an excellent example of timing budget measurements that can reduce the impact of noise in your system.
Garmin's GPSMAP-76S: Location, location, location
Teardown  
7/10/2002   Post a comment
Garmin's latest sensor-laden global positioning system handheld foreshadows technology that's likely to infiltrate more of our personal electronics.
USB 2.0 Multi-TT Hubs Outperform Single-TT Hubs
News & Analysis  
7/10/2002   Post a comment
Since the adoption of the 2.0 specification, USB is quickly emerging as a main way to link portable devices. But to be successful, designers should turn to multi-transaction translators in hub architectures.
I/O buffer timing ensures board Signal Integrity
News & Analysis  
7/9/2002   Post a comment
As the speed of modern high-performance buses increases to 400 MHz and beyond, signal integrity concerns have a large and increasing effect on timing closure.
VSIA guidelines assist SoC Signal Integrity
News & Analysis  
7/9/2002   Post a comment
Authors and integrators of intellectual property (IP) are trying to tape out chips without real verification of chip-level signal integrity matters. EDA solutions are complex and inadequate, with capacity-limited extraction tools that run out of steam well before system-on-chip (SoC) design sizes are met.
Smart wireless products demand complex power management
Design How-To  
7/9/2002   Post a comment
Cellular telephone technology is one of the best success stories of recent years with its capability to keep the user working untethered for an entire day, and requiring only a single overnight recharge.
Small gains in power efficiency now, bigger gains tomorrow
Design How-To  
7/9/2002   Post a comment
Consumers expect that advanced 2.5G and 3G cellular phones will come in the same form factors and exhibit the same battery life as existing 2G cellular phones.
Page 1 / 2   >   >>


Flash Poll
EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Rishabh N. Mahajani, High School Senior and Future Engineer

Future Engineers: Don’t 'Trip Up' on Your College Road Trip
Rishabh N. Mahajani, High School Senior and Future Engineer
3 comments
A future engineer shares his impressions of a recent tour of top schools and offers advice on making the most of the time-honored tradition of the college road trip.

Max Maxfield

Juggling a Cornucopia of Projects
Max Maxfield
7 comments
I feel like I'm juggling a lot of hobby projects at the moment. The problem is that I can't juggle. Actually, that's not strictly true -- I can juggle ten fine china dinner plates, but ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
37 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Karen Field

July Cartoon Caption Contest: Let's Talk Some Trash
Karen Field
140 comments
Steve Jobs allegedly got his start by dumpster diving with the Computer Club at Homestead High in the early 1970s.

Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)