inSilicon rolls out latest core for single-chip USB 2.0 designs News & Analysis 1/16/2001 Post a comment SAN JOSE --In a move to support single-chip designs for the Universal Serial Bus 2.0 specification, inSilicon Corp. today announced its initial USB 2.0 physical layer (PHY) core aimed at reducing component count in systems with integrated mixed-signal functions. The mixed-signal USB 2 PHY core results from inSilicon's collaboration with Tality LLP, a design services supplier spun out of Cadence Design Systems Inc.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.