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posted in January 2001
inSilicon rolls out latest core for single-chip USB 2.0 designs
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1/16/2001   Post a comment
SAN JOSE --In a move to support single-chip designs for the Universal Serial Bus 2.0 specification, inSilicon Corp. today announced its initial USB 2.0 physical layer (PHY) core aimed at reducing component count in systems with integrated mixed-signal functions. The mixed-signal USB 2 PHY core results from inSilicon's collaboration with Tality LLP, a design services supplier spun out of Cadence Design Systems Inc.

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