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Wearables & IoT to Alter Electronic Design Process
10/6/2015   Post a comment
Living small requires a lot of planning. Engineers will need all the help they can get designing for the Internet of Things.
New Funding Brings Aquantia Near $200 Million
News & Analysis  
10/5/2015   2 comments
Funding round worth $37 million brings Ethernet chip vendor to $199 million total over 10 years.
Put FPGAs In Your SoCs
News & Analysis  
10/2/2015   5 comments
Flex Logix has a new type of FPGA that nearly doubles the number of usable gates per chip. The FPGAs eliminate more than 20% of the room needed for interconnect and switches, and now have nearly 50% more room for gates.
Startup Raises Online Tool Debate
News & Analysis  
9/30/2015   Post a comment
Upverter upgraded its online service for circuit-board designers, raising questions about the outlook for cloud-based design.
TSMC Preps 10nm, Tunes 16nm
News & Analysis  
9/17/2015   7 comments
The world’s largest chip foundry said it will start “risk” production in 10nm late this year while it fine tunes its 16nm process and plans a basket of IoT offerings.
Dresden Memory Startup To Debut At Semicon Europa
News & Analysis  
9/15/2015   4 comments
A startup company that is working on a ferroelectric non-volatile memory technology based on hafnium oxide is set to make its debut at the Semicon Europa exhibition taking place in Dresden, Germany, October 6 to 8.
Post-Silicon Tech Compared
News & Analysis  
9/9/2015   4 comments
The Semiconductor Research Corporation is creating a joint benchmarking effort with Georgia Tech to guide post-silicon era electronics development at IBM, Intel, Freescale and Texas Instruments.
Flextech Guru Helps U.S. Stretch
News & Analysis  
9/3/2015   2 comments
The head of a new initiative to give the U.S. a lead in flexible hybrid electronics talks about the technology, markets and politics of the $165 million effort.
Nanotech Hub Targets 7nm, Beyond
8/27/2015   2 comments
We toured the College of Nanoscience and Engineering, part of a State University of New York campus, a hub for advanced semiconductor manufacturing research in areas such as lithography, 450mm wafers, and new materials as well as photonics, biotech and workforce development.
Giga-Scale Challenges Plague Memory Design
8/27/2015   Post a comment
Advanced designs are more complex and larger than ever before and designers are balancing between accuracy and performance for large scale memory simulation and verification, fine-tuning options and settings for each circuit type
The Power of Dynamic Voltage Frequency Scaling
8/20/2015   3 comments
If dynamic behavior could be adjusted to fit the task at hand in consumer electronics, think of the power that could be saved.
Intel CEO Sees A Bright Future For IoT, Developers
News & Analysis  
8/19/2015   Post a comment
Tiny computers, real-time depth sensing, and breakthrough memory technology are among the innovations featured at this year's Intel Developer Forum. CEO Brian Krzanich detailed how connected devices will change the way we all do business.
Developing Prototype Circuits from Home
Engineering Investigations  
8/18/2015   4 comments
Regardless of whether you are independent or employed by a company, there are many advantages to developing a prototype on your own.
Agile Design for Hardware, Part III
8/3/2015   4 comments
In the final installment of a three-part series, two Berkeley professors describe Chisel, a new programming tool suitable for Agile hardware development.
Making a Difference Still Does Make a Difference
7/24/2015   Post a comment
The quality of products engineers and designers can make is only limited by the quality of tools that are available to them. Making a difference in the quality and productivity of ASIC and FPGA designers is key.
10 Views of Semicon West
7/17/2015   4 comments
Systems-in-package could prop up a semiconductor industry falling off Moore’s Law, but hopes IoT will be the next driver may be too optimistic.
Ex-IBMer Fired Up for Foundry
News & Analysis  
7/16/2015   11 comments
Globalfoundries’ new CTO Gary Patton talks about life after IBM and the challenging road ahead for semiconductor makers.
High Customer Interest in FD-SOI, GloFo Says
News & Analysis  
7/16/2015   2 comments
Customers are already lining up to use the 22nm fully depleted silicon-on-insulator (SOI) technology announced by Globalfoundries earlier this week, according to a company executive.
Veteran EDA Analyst Gary Smith Dies
News & Analysis  
7/7/2015   9 comments
Memorial set for July 12 for man who was the voice of EDA for more than three decades.
8 FD-SOI Questions You're Afraid to Ask
6/30/2015   13 comments
Paul Boudre, CEO of Soitec, told us last week in Grenoble, “Evidence [for FD-SOI’s advantages] is there. But some choose not to see it.”
Synopsys Acquires Elliptic Technologies, Beefs up Security
News & Analysis  
6/30/2015   Post a comment
Synopsys, Inc. is acquiring security intellectual property company Elliptic Technologies.
EDA Retrospective: 30+ Years of Highlights, Lowlights
6/24/2015   3 comments
Technology journalist Richard Goering is about to retire after 30 years covering electronic design automation. He sums up some important EDA milestones.
IBM Demos III-V FinFETs on Silicon
News & Analysis  
6/18/2015   3 comments
IBM has found a way to use confined epitaxial overgrowth (CELO) to build III-V FinFETs on silicon wafers using standard CMOS processing.
10nm Chips Promise Lower Costs
6/15/2015   38 comments
The challenges in the supply chain logistics for semiconductors continue to increase, but the 10nm node will give one more opportunity to gain large benefits from technology scaling.
Smart Glasses Strap On AR
News & Analysis  
6/10/2015   Post a comment
Emerging technologies like AR comes with a series of challenges and opportunities, executives from smart glasses and AR device companies said during a session. Still, as additional use cases develop the possibilities are endless.
Simulate Your Buck-Converter Control Loop
6/8/2015   2 comments
Stabilizing the control loop of a voltage-mode (VM) or current-mode (CM) buck converter can be confusing, even intimidating, to non-power engineers. This article shows simple VM and CM SPICE simulation models that can predict your results with accuracy and provide a deeper understanding of key power block functions.
IBM Renting Its EDA Tools
News & Analysis  
6/7/2015   5 comments
Ever since IBM started designing systems over 100 years ago, it has used it own internally developed toolkits, the envy of designers who have to use brand-x electronic design automation (EDA) suites. Now IBM is renting the use of its famous tools online at one-half the price of licensing brand-x tools.
FPGAs Ride HP’s Moonshot
News & Analysis  
5/28/2015   18 comments
SRC Computers announced a new FPGA server card that Hewlett-Packard will sell as an option for its processor-agnostic Moonshot servers.
SoC From Russia With MIPS
News & Analysis  
5/27/2015   7 comments
Baikal Electronics of Russia, announced its T1, the first chip to use MIPS Warrior cores, will take on Broadcom and others in WiFi routers and home gateways.
It’s Time to Stop Kicking the EDA Dog
5/25/2015   Post a comment
It’s incumbent on IP vendors to deliver higher quality designs that enable a smoother back-end process.
eSilicon Brings Virtualization to Online Portal
News & Analysis  
5/19/2015   Post a comment
An IC designers’ job is mired in “what if’s.” eSilicon wants to make the ASIC designer’s decision process as painless as possible. The company is unveiling Tuesday a new online tool called “Optimizer.”
Model Trains Put Strain on Batteries, AC Power
5/13/2015   10 comments
Sometimes the obvious, free, and available power rail is not the right path for reliable power delivery, but you stick with it until new technologies allow better alternatives.
Engineer Building Google for Chips
News & Analysis  
5/1/2015   25 comments
An engineer-turned-entrepreneur aims to develop a Google for semiconductors, making it easier for engineers to find and evaluate chips.
Microsoft Demos HoloLens
News & Analysis  
4/29/2015   Post a comment
In what was otherwise a developer lingo-heavy event, Microsoft showcased updates to its HoloLens virtual reality platform running on Windows 10. The demos were part of Microsoft’s Build developer conference, held here April 29-March 1.
High-End PCB Design Made Affordable
News & Analysis  
4/28/2015   5 comments
Mentor's new PADS family targets independent engineers with lower cost and more powerful printed circuit board design capabilities.
Smartwatch Uptick in Mobile Slump
News & Analysis  
4/23/2015   3 comments
Smartwatches could grow to sales of 400 million units a year by 2019 when smartphone and tablet sales slump to single-digit levels, said a market watcher.
EDA Tool Speeds FinFET Design
News & Analysis  
4/22/2015   Post a comment
Mentor Graphics new Calibre xACT tool extracts parasitic capacitance, resistance and inductance quickly and accurately.
Odds of Success of Mie Fujitsu, Japan’s Pure-Play Foundry
News & Analysis  
4/16/2015   2 comments
Mie Fujitsu Semiconductor is a foundry born from Fujitsu’s lack of any better options. Its genesis raises questions about the odds of Mie Fujitsu’s survival. We asked Mie Fujitsu President hard questions.
Samsung Describes Road to 14nm
News & Analysis  
4/16/2015   2 comments
A Samsung executive described the company's road to it 14nm FinFET process used for the Exynos chip in its latest smartphones.
Prototyping Fest Changes SF Streets
4/10/2015   Post a comment
The Market Street Prototyping Festival is underway and has transformed sections of San Francisco's main thoroughfare into a maker/designer space.
Mentor Graphics Drives ISPD Contest
News & Analysis  
4/6/2015   1 comment
The contest winners for the Association for Computing Machinery's ACM's) International Symposium on Physical Design (ISPD) are enumerated as well as Kurt Antreich who was honored for his outstanding achievements.
Analog EDA Finally Automated
News & Analysis  
4/1/2015   9 comments
Reutlingen University has created automated techniques for designing analog circuits, the technology for which it transferred to Cadence, and Rob Rutenbar at the University of Illinois in Urbana described how to convince analog designers use the new tools.
Power & Signal Over A Single Wire Do More With Less
3/31/2015   1 comment
If power together with signal is your goal, there are a number of different ways to get it done -- assuming ludicrous speed isn't a requirement, of course.
Nanolaser Enables On-Chip Photonics
News & Analysis  
3/26/2015   2 comments
Researchers at the University of Washington and Stanford has created a new type of laser for easier on-chip communications using electro-modulation.
Ericsson on Power: We Need To Rethink Structure
News & Analysis  
3/25/2015   Post a comment
Next-generation cellular communications will require a drastic reduction in energy consumption, something researchers at Ericsson are calling “ultra-lean transmission.” A focus on power management software could alleviate some of these issues.
Altium Updates High-Speed PCB Design Tool
News & Analysis  
3/3/2015   Post a comment
Altium next update to its flagship PCB design tool, Altium Designer 15.1, introduces new features the company says improves design productivity, documentation outputs, and high-speed design efficiency.
Embedded Job Market Expands, But Boomers Feel the Squeeze
News & Analysis  
3/2/2015   12 comments
By almost any measure, the job market appears to be looking very good right now for embedded engineers. But not for everyone.
Open-Silicon: ‘No Software Runs Without Hardware’
News & Analysis  
2/9/2015   1 comment
As the valuation of high-tech companies goes increasingly lopsided -- disproportionately favoring the software business -- the obvious question is: Who nowadays is willing to get their hands dirty designing high-cost, low-margin hardware?
16 Takeaways from DesignCon 2015
2/2/2015   2 comments
At DesignCon 2015 I heard what’s happening in high-speed chip and board interface design including issues with 56G, silicon photonics and optical backplanes.
What Drove CES 2015 Innovation? IP and IP Subsystems
1/28/2015   8 comments
How do we manage all those blocks in an age of exploding block usage?
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