How poor packaging kills good PCB designs News & Analysis 1/30/2004 Post a comment Package parasitic inductance has a huge impact on PCB design and performance. In this excerpt from his recent book, PCB design guru Lee Ritchey (right) shows how to avoid VCC and ground bounce caused by poor IC package design.
Layout, synthesis sales boost Magma results News & Analysis 1/30/2004 Post a comment Citing strong sales in IC physical design and synthesis, Magma Design Automation exceeded Wall Street consensus for its fiscal 2004 third quarter, ending Dec. 31, 2003. The company posted a profit of $0.16 per share on revenue of $31.1 million.
Synopsys acquires ADA for analog boost News & Analysis 1/28/2004 Post a comment Making further inroads into the analog design market, Synopsys Inc. Wednesday (Jan. 28) announced its intention to acquire the assets of Analog Design Automation (ADA, Ottawa, Ontario) for an undisclosed sum. ADA provides analog optimization software.
Synopsys buys Analog Design Automation News & Analysis 1/28/2004 Post a comment Moving to strengthen its analog and mixed-signal offerings, Synopsys Inc. has announced its intention to acquire the assets of Analog Design Automation Inc. (ADA), a provider of automated circuit optimization software. Synopsys will sell the technology standalone and integrate it into its HSpice and NanoSim simulators.
Mentor Q4 suggests selective EDA recovery News & Analysis 1/27/2004 Post a comment The EDA industry isn't enjoying a broad-based recovery yet, but selected product and technology areas are strong, according to Mentor Graphics executives reporting that company's fourth-quarter 2003 results Tuesday (Jan. 27). Strength in IC physical verification, test, and cabling helped Mentor achieve record quarterly revenue of $202 million.
0-In revamps verification products News & Analysis 1/26/2004 Post a comment Revamping its assertion-based verification tools, 0-In Design Automation Inc. will introduce the Archer Verification system this week, offering three configurations aimed at different methodologies. The tools incorporate and replace the individual tools in 0-In's current Assertion-Based Verification (ABV) tool suite, the company said.
Startups took center stage in '03 News & Analysis 1/26/2004 Post a comment I thought we were writing an awful lot of stories about EDA startups in 2003, and I've just confirmed it. My file of 2003 startups includes 46 companies, about as many as 2002 and 2001 combined. There is both good and bad news behind this surge.
Startup analyzes algorithms for power consumption News & Analysis 1/23/2004 Post a comment Startup PowerEscape Inc. is releasing what it calls the first commercial tools to analyze software algorithms to reduce a system's power consumption. PowerEscape Analyzer and PowerEscape Analyzer+Cache have demonstrated power reductions of more than 80 percent, the company said.
How SystemVerilog aids design and synthesis News & Analysis 1/23/2004 Post a comment SystemVerilog is primarily known for the new features it brings to verification engineers, but there are also some important additions for designers, according to Synopsys' Karen Pieper (right). In this article, she shows how structures, interfaces, and new types of always blocks can speed RTL design and synthesis.
DAC 'trip report' evaluates EDA tools News & Analysis 1/22/2004 Post a comment What may be the most comprehensive user evaluation of EDA tools ever is available on-line in a long-awaited Design Automation Conference (DAC) "trip report" compiled by John Cooley, moderator of the E-Mail Synopsys User's Group. In it, 492 engineers provide no-holds-barred reviews of tools from over 80 vendors.
Cadence moves to 64-bit Linux News & Analysis 1/21/2004 Post a comment With two separate announcements this week (Jan. 21), Cadence Design Systems is rolling out its first support for 64-bit Linux. A Monday announcement cited support for Intel Itanium 2-based systems, and a Wednesday announcement pledged support for AMD64 Opteron processors.
EDA startup names management team News & Analysis 1/21/2004 Post a comment Startup Silicon Dimensions Inc. (SDI), which promises a unique set of "design closure" tools for complex ICs, has announced its company launch and management team. Based in Marlborough, Mass., the company combines EDA and semiconductor expertise.
HP adopts OpenAccess for 90nm flow News & Analysis 1/16/2004 Post a comment To resolve interoperability problems, Hewlett-Packard recently deployed the OpenAccess database in its synthesis, placement and routing flow for a 90nm chip design. In this feature, EDA manager Scott Markinen and co-authors show why and how they did it, and report what they encountered.
Islands in the power management storm News & Analysis 1/15/2004 Post a comment A perfect storm of forces-mobility, process technology and system-on-chip complexity-are combining to create a tsunami of challenges for SoC designers who need to manage dynamic power consumption and static leakage at 130- and 90-nm process technologies.
Synopsys lawsuit impacts Nassda quarterly results News & Analysis 1/15/2004 Post a comment Full-custom simulator vendor Nassda Corp. hit projected numbers posting revenues of $9.7 million for its fiscal first quarter of 2004, ending Dec. 31, 2003, but the specter of its lawsuit with Synopsys is significantly impacting earnings, executives said.
Eclipse concepts yield reliable software News & Analysis 1/12/2004 Post a comment Eclipse has a strong reputation as a reliable and high-quality platform, the result of an agile development process with unit testing and refactoring as well as conceptualization of a flexible and extensible architecture.
Agilent adds Verilog-A support News & Analysis 1/7/2004 Post a comment Claiming a significant advantage over proprietary models, Agilent Technologies has introduced Verilog-A support for its RF Design Environment (RFDE) 2003C and Advanced Design System (ADS) 2003C EDA tools. Verilog-A is a standard language that lets users develop analog behavioral and compact device models.
Evaluating and improving emulator performance News & Analysis 1/3/2004 Post a comment Specifications and performance metrics for emulators are confusing and inconsistent. In this tutorial, EVE's Lauro Rizzatti and Zaiq Technologies' Damian Deneault show you how to evaluate emulator speed, and improve it dramatically with transaction-based emulation.