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posted in January 2005
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'Tuned' Embedded-Memory Test and Repair Improves Yield, Reliability
Design How-To  
1/31/2005   Post a comment
Because embedded memories impact the overall yield of a chip quite dramatically, it is necessary to have a robust test and repair methodology to produce high quality chips with maximum yield.
EDA models falling short for rapid production ramp ups
News & Analysis  
1/31/2005   Post a comment
Better models and analysis tools don't always translate into quick production ramp ups, an EDA industry executive told the DesignCon 2005 meeting.
PCB 'synthesis' product automates component placement
News & Analysis  
1/31/2005   Post a comment
A startup launched by Carnegie Mellon University (CMU) researchers is preparing CircuitSpace, a pc-board "synthesis" tool that claims to be the first to bring user-assisted automated component placement to PCB designers.
Embedded-Systeme im Fokus der DATE
Product News  
1/31/2005   Post a comment
Die europäische Halbleiter-Designmesse DATE verschiebt ihren Fokus zunehmend in Richtung auf die Entwicklung von Plattformen für Embedded-Systeme. Dabei gewinnt das Thema Software unverkennbar an Bedeutung.
Magma legt letzte Hand an eigene EDA-Suite
News & Analysis  
1/28/2005   Post a comment
Mit der ersten Software für die Halbleitergenerationen ab 65 Nanometer überholt der Softwarehersteller Magma Design Automation seine Konkurrenten.
Magma reveals next-gen IC design suite
News & Analysis  
1/28/2005   Post a comment
Magma Design Automation is about to leapfrog its competitors with the first IC design system aimed at 65 nanometers and below, according to Rajeev Madhavan, Magma CEO. At Magma's quarterly earnings conference call Thursday (Jan. 27), Madhavan offered a surprise preview of Cobra, an internal development effort that promises a number of technology breakthroughs.
Mentor, Magma report sales gains
News & Analysis  
1/27/2005   Post a comment
Electronic design automation suppliers Mentor Graphics Corp. and Magma Design Automation Inc. saw year-over-year sales gains in their December fiscal quarters.
Les recettes de Verisity progressent à l’approche de l’acquisition de la société
News & Analysis  
1/26/2005   Post a comment
Le fabricant d’outils de vérification Verisity Ltd. annonce une hausse de 45 %, en glissement annuel, de ses recettes pour le quatrième trimestre 2004. Cependant, les dirigeants de la société restent très discrets quant à son acquisition imminente par Cadence Design Systems.
Cadence erweitert Unterstützung für Wireless-Designs
News & Analysis  
1/25/2005   Post a comment
Eine bessere Unterstützung für den Entwurf von Hochfrequenz- und Mixed-Signal-Schaltkreisen bietet jetzt die Design-Plattform Virtuoso des Softwareherstellers Cadence Design Systems.
MathWorks adds fixed-point design and simulation to DSP tool
News & Analysis  
1/25/2005   Post a comment
The MathWorks announced the availability of the new Fixed-Point Toolbox and Simulink Fixed Point, bringing fixed-point design capabilities to MATLAB and enhanced fixed-point simulation in Simulink.
V6 Automation Tools Speed SOC and Embedded System Design by 'Several Orders of Magnitude'
Product News  
1/24/2005   Post a comment
New Compiler, Instruction-Set Simulator Make it Easier, Faster to Design With Configurable Processors than Custom Logic
Synplicity upgrades FPGA synthesis
News & Analysis  
1/24/2005   Post a comment
Synplicity Inc. has released a new version of its Synplify Pro FPGA synthesis tool boasting major run time and quality of results improvements largely gained through close integration with third-party formal verification, place & route, and debugging products. The latest version also features support for an early subset of System Verilog.
Tharas spins four-state simulation add-on for accelerator
News & Analysis  
1/24/2005   Post a comment
Hardware acceleration startup Tharas Systems Inc. has released a Verilog four-state logic simulation add-on to its Hammer hardware accelerator.
Arena offers PLM tool free for one year
News & Analysis  
1/24/2005   Post a comment
In an attempt to increase adoption, Product Lifecycle Management tool startup Arena Solutions Inc. is offering its Arena PLM Workgroup Edition, an entry-level version of its PLM solution, at no cost for the first year.
Blue Pearl releases RTL optimizer
News & Analysis  
1/24/2005   Post a comment
EDA startup Blue Pearl Software Inc. has announced the release of its first product, Indigo RTL Analysis, for rapid functional closure.
Techniques for reducing signal-integrity pessimism
News & Analysis  
1/24/2005   Post a comment
Undue signal-integrity pessimism is killing design productivity, says Cadence Design Systems' Rahul Deokar (right). In this article, he discusses the causes of pessimism and reviews methods of reducing false violations.
Property checker verifies false paths
News & Analysis  
1/24/2005   Post a comment
Claiming a new capability for the EDA industry, Averant Inc. this week is introducing an automatic verification tool for timing exceptions, including false and multicycle paths.
Summit releases text-based SystemC design tool
News & Analysis  
1/24/2005   Post a comment
Summit Design Inc. will release this week a front end text-based SystemC design Environment called Vista that allows engineers familiar with HDL design to come up to speed on C++/SystemC design techniques.
CoWare SPW supports latest release of Cadence Virtuoso
News & Analysis  
1/24/2005   Post a comment
CoWare Inc. has announced that it has integrated its SPW digital signal processing (DSP) application design tool with the new RF design features that Cadence's Design Systems Inc.'s has built into the latest release of its Virtuoso custom design platform.
Don't pay too much for mixed-signal tools
News & Analysis  
1/22/2005   Post a comment
Do you really need high-end analog design tools and unified databases? Probably not, says John Tanner, president of Tanner Research.
TransEDA ajoute le support de SystemVerilog à deux de ses outils
News & Analysis  
1/21/2005   Post a comment
TransEDA, leader des solutions de vérification de systèmes électroniques prêtes à l’emploi, vient d’annoncer le support de SystemVerilog dans ses nouvelles versions d’outils VN-Cover et VN-Check.
Comment améliorer la productivité de la vérification ?
News & Analysis  
1/21/2005   Post a comment
Le temps passé à la vérification dépasse désormais le temps nécessaire à la conception, jusqu’à 70% de l’effort total de développement. Pourtant, le coût des pannes ne cesse d’augmenter. Le problème est que les méthodes de vérification actuelles n’offrent ni l’efficacité ni la productivité escomptées par les concepteurs pour maintenir la cadence nécessaire face à des puces d’une complexité croissante, notamment pour la conception au 90 nanomètres et au-delà.
Virage posts solid second quarter
News & Analysis  
1/20/2005   Post a comment
On the heels of the acquisition of its main competitor, Artisan Components, by ARM Ltd., library vendor Virage Logic Inc. posted record revenue in the first quarter of 2005.
Users speak up on Cadence's bid for Verisity
News & Analysis  
1/19/2005   Post a comment
Users feelings are mixed but generally positive regarding Cadence Design Systems pending $285 million acquisition of testbench generation and emulation tool vendor Versity Ltd., according to a survey newly posted on the Deepchip.com Web site.
EDA startup Ammocore headed for liquidation
News & Analysis  
1/19/2005   Post a comment
Netlist to routing EDA startup Ammocore Inc. is headed for liquidation.
Cadence releases design constraint checker
News & Analysis  
1/18/2005   Post a comment
Cadence Design System Inc. has released a new formal analysis tool that generates, analyzes and validates the quality of design constraints designers use to run synthesis, timing analysis and place and route tools.
SystemC synthesis under $2,000 debuts
News & Analysis  
1/18/2005   Post a comment
British EDA startups Orange Tree Technologies and SystemCrafter have teamed to make SystemC synthesis more affordable for the masses.
Model-Based Development with Virtual Prototypes
Design How-To  
1/18/2005   Post a comment
Automobiles contain many complex electronic systems. Managing these along with time-to-market and quality, dictates a new approach, yet one that is as old as the industry itself.
Tharas offers Axis replacement plan
News & Analysis  
1/18/2005   Post a comment
Tharas Systems Inc. is unveiling a replacement program aimed at addressing the expected phaseout of the Axis line of verification products when Cadence Design Systems Inc. completes its planned acquisition of Verisity Ltd.
How ESL becomes a business imperative
News & Analysis  
1/17/2005   Post a comment
ESL isn't just about chip design, says Summit Design's Jon McDonald. He outlines four "indicators" that could make it a business imperative for many types of system designs.
Embedded FingerChip Sensor Enables Enhanced Security
Product News  
1/17/2005   Post a comment
Designers can now added finger print sensors to their embedded designs.
USB Host Mass Storage Reference Design Kit for Embedded Designs
Product News  
1/17/2005   Post a comment
Low-Cost Kit Enables PC-Free Communication With USB Mass Storage
Block-Based Design Entry Tool for Imaging and Video Applications
Product News  
1/17/2005   Post a comment
Delivers IP for Rapid System Implementation through C-based Synthesis.
in-SYNC Program Brings Celoxica C Based Hardware Compilers to Design Tools to the Synopsys Design Compiler Family
Product News  
1/17/2005   Post a comment
Development formalizes the interoperability between Celoxica's Agility Compiler and DK Design Suite
EDA startup preps sequential equivalency checker
News & Analysis  
1/17/2005   Post a comment
Promising to ensure that high-level models match their RTL implementations, startup Calypto Design Systems this week is announcing its mission and its plans to field a sequential equivalency checker. The company will help enable the move to system-level design, said Devadas Varma, president and CEO.
Reducing false errors in clock-domain crossing analysis
News & Analysis  
1/17/2005   Post a comment
Clock domain crossings (CDCs) can cause serious design problems, but analysis tools typically report lots of false positives. Atrenta CTO Bernard Murphy (right) reviews methods of minimizing false domain crossings.
Cadence rachète Verisity pour 258 millions de dollars
News & Analysis  
1/14/2005   Post a comment
Cadence Design Systems Inc. a signé un accord définitif visant à racheter Verisity Ltd. (Mountain View, Californie) pour 12 dollars par action, soit une transaction au comptant estimée à 285 millions de dollars.
Cree revenue slightly off Wall Street estimates in second quarter
News & Analysis  
1/13/2005   Post a comment
Semiconductor vendor Cree Inc. barely missed Wall Street revenue estimates reporting, revenue of $97.4 million for the second quarter of fiscal 2005.
Cadence übernimmt Verisity
News & Analysis  
1/13/2005   Post a comment
In der Designautomation steht eine wichtige Übernahme bevor: Cadence Design Systems will Verisity schlucken. Das Interesse gilt vor allem Verisitys Software für Chip-Verifikation und -Prototyping.
Cadence buys Verisity for $285 million
News & Analysis  
1/13/2005   Post a comment
Cadence Design Systems Inc. has signed a definitive agreement to acquire Verisity Ltd. for $12 per share in an all cash deal.
With acquisition pending, Nassda returns to profitability
News & Analysis  
1/12/2005   Post a comment
Nassda Corp. returned to profitability in the first quarter of 2005, posting revenue of $11.3 million, an increase of 2 percent from $11 million for the quarter ended Sept. 30, 2004.
RF vendor changes name, upgrades ESL tool
News & Analysis  
1/12/2005   Post a comment
RF tool vendor Eagleware Corp. has announced it has changed its name to Eagleware-Elanix Corp., reflecting its merger last December with ESL tool vendor Elanix Corp.
Synopsys execs get smaller bonuses in rough year
News & Analysis  
1/12/2005   Post a comment
During a year in which Synopsys Inc. fell from EDA industry's top spot and misjudged earnings twice, the company's top officers still received sizable year-end bonuses -- albeit smaller ones than in past years.
Synopsys modifie ses prévisions pour le 1er trimestre et l’ensemble de l’exercice 2005
News & Analysis  
1/12/2005   Post a comment
Synopsys Inc. vient de revoir à la baisse son objectif de bénéfices par action pour l’exercice 2005 en raison d’un ajustement de la prise en compte des actifs, et de revoir à la hausse ses prévisions de recettes et de bénéfices pour le premier trimestre 2005.
Jasper acquires formal tool vendor Safelogic
News & Analysis  
1/12/2005   Post a comment
Formal verification tool vendor Jasper Design Automation Inc. has acquired Swedish formal verification tool vendor Safelogic for an undisclosed amount.
OCP-IP upgrades core to bus validation tool
News & Analysis  
1/11/2005   Post a comment
The latest version of Open Core Protocol International Partnership's (OCP-IP) front end OCP validation tool complies with and supports the OCP 2.0 specification.
FTC seeks info on Synopsys' pending acquisition of Nassda
News & Analysis  
1/11/2005   Post a comment
The Federal Trade Commission has requested further information from Synopsys Inc. and Nassda Corp. regarding Synopsys' pending acquisition of Nassda, the companies announced.
Mentor guidance moves higher for fourth quarter revenue, bookings
News & Analysis  
1/11/2005   Post a comment
Mentor Graphics preannounced that its fourth quarter revenue and bookings will exceed previous guidance.
Un Français à la tête de VaST Systems
News & Analysis  
1/11/2005   Post a comment
Mi-décembre, le Français Alain Labat démissionne de son poste de directeur général de TeraSystems Inc pour poursuivre de nouveaux intérêts. Il fait aujourd’hui la lumière sur ses intentions réelles en acceptant les fonctions de Président-directeur général de VaST Systems Technology Corporation, leader dans le domaine de la conception de systèmes embarqués et d’outils de développement.
How to boost verification productivity
News & Analysis  
1/10/2005   Post a comment
Assertion-based verification (ABV), testbench automation, and coverage-driven verification can be combined to make verification more effective, says Mentor Graphics' Robert Hum.
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